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74F378SJXNSN/a7500avai Parallel D-Type Register with Enable
74F378SJXFAIN/a4002avai Parallel D-Type Register with Enable
74F378SJXNS ?N/a447avai Parallel D-Type Register with Enable


74F378SJX , Parallel D-Type Register with EnableFeaturesThe 74F378 is a 6-bit register with a buffered common 6-bit high-speed parallel registerEn ..
74F378SJX , Parallel D-Type Register with Enable74F378 Parallel D-Type Register with EnableApril 1988Revised August 199974F378Parallel D-Type Regis ..
74F378SJX , Parallel D-Type Register with EnableFunctional Description Truth TableThe 74F378 consists of six edge-triggered D-type flip-flopsInputs ..
74F379 ,Quad Parallel Register with EnableFunctional Description Truth TableThe 74F379 consists of four edge-triggered D-type flip-Inputs Out ..
74F379 ,Quad Parallel Register with Enablefeatures

74F378SJX
Parallel D-Type Register with Enable
74F378 Parallel D-Type Register with Enable April 1988 Revised August 1999 74F378 Parallel D-Type Register with Enable General Description Features The 74F378 is a 6-bit register with a buffered common � 6-bit high-speed parallel register Enable. This device is similar to the 74F174, but with com- � Positive edge-triggered D-type inputs mon Enable rather than common Master Reset. � Fully buffered common clock and enable inputs � Input clamp diodes limit high-speed termination effects � Full TTL and CMOS compatible Ordering Code: Order Number Package Number Package Description 74F378SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F378SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F378PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 DS009526
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