74AUP1G885GM Fast Delivery |IC PHOENIX CO.,LIMITED

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74AUP1G885GM
Low-power dual function gate
1. General description
The 74AUP1G885 provides two functions in one device. The output state of the outputs
(1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean
function: 1Y = A C. The output 2Y provides the Boolean function: 2Y =A B +AC.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 0.8 Vto 3.6V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 Vto 1.3 V) JESD8-11 (0.9 Vto 1.65V) JESD8-7 (1.2 Vto 1.95V) JESD8-5 (1.8 Vto 2.7V) JESD8-B (2.7 Vto 3.6V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
74AUP1G885
Low-power dual function gate
Rev. 9 — 31 January 2013 Product data sheet
NXP Semiconductors 74AUP1G885
Low-power dual function gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74AUP1G885DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74AUP1G885GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 1.95 0.5 mm
SOT833-1
74AUP1G885GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; terminals; body 1.351 0.5 mm
SOT1089
74AUP1G885GD 40 Cto +125C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74AUP1G885GM 40 C to +125C XQFN8 plastic, extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
74AUP1G885GN 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.21.0 0.35 mm
SOT1116
74AUP1G885GS 40 C to +125C XSON8 extremely thin small outline package; no leads; terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
74AUP1G885DC pS8
74AUP1G885GT pS8
74AUP1G885GF 58
74AUP1G885GD pS8
74AUP1G885GM pS8
74AUP1G885GN 58
74AUP1G885GS 58
NXP Semiconductors 74AUP1G885
Low-power dual function gate
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin description
A, B, C 1, 2, 6 7, 6, 2 data input
GND 4 4 ground (0 V)
n.c. 5 3 not connected, 2Y 7, 3 1, 5 data output
VCC 8 8 supply voltage
NXP Semiconductors 74AUP1G885
Low-power dual function gate
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level.
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 4. Function table[1]
LLLLL LLLH LLH
HHL L H
LLH LL HHL HHL H
HHHHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +4.6 V
IOK output clamping current VO <0V 50 - mA output voltage Active mode and Power-down mode [1] 0.5 +4.6 V output current VO =0 VtoVCC - 20 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [2] -250 mW
NXP Semiconductors 74AUP1G885
Low-power dual function gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Operating conditions
VCC supply voltage 0.8 3.6 V input voltage 0 3.6 V output voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 3.6 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall
rate
VCC= 0.8 V to 3.6V - 200 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = 25 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70  VCC -- V
VCC = 0.9 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30  VCCV
VCC = 0.9 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.75  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.11 - - V
IO = 1.9 mA; VCC = 1.65 V 1.32 - - V
IO = 2.3 mA; VCC = 2.3 V 2.05 - - V
IO = 3.1 mA; VCC = 2.3 V 1.9 - - V
IO = 2.7 mA; VCC = 3.0 V 2.72 - - V
IO = 4.0 mA; VCC = 3.0 V 2.6 - - V
NXP Semiconductors 74AUP1G885
Low-power dual function gate
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.2 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 0.5 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V
[1] -- 40 A input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC -0.6 -pF output capacitance VO = GND; VCC = 0 V - 1.3 - pF
Tamb = 40 C to +85C
VIH HIGH-level input voltage VCC = 0.8 V 0.70  VCC -- V
VCC = 0.9 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30  VCCV
VCC = 0.9 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.7  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.03 - - V
IO = 1.9 mA; VCC = 1.65 V 1.30 - - V
IO = 2.3 mA; VCC = 2.3 V 1.97 - - V
IO = 3.1 mA; VCC = 2.3 V 1.85 - - V
IO = 2.7 mA; VCC = 3.0 V 2.67 - - V
IO = 4.0 mA; VCC = 3.0 V 2.55 - - V
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G885
Low-power dual function gate
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.6 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 0.9 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V
[1] -- 50 A
Tamb = 40 C to +125C
VIH HIGH-level input voltage VCC = 0.8 V 0.75  VCC -- V
VCC = 0.9 V to 1.95 V 0.70  VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.25  VCCV
VCC = 0.9 V to 1.95 V - - 0.30  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.11- - V
IO = 1.1 mA; VCC = 1.1 V 0.6  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 0.93 - - V
IO = 1.9 mA; VCC = 1.65 V 1.17 - - V
IO = 2.3 mA; VCC = 2.3 V 1.77 - - V
IO = 3.1 mA; VCC = 2.3 V 1.67 - - V
IO = 2.7 mA; VCC = 3.0 V 2.40 - - V
IO = 4.0 mA; VCC = 3.0 V 2.30 - - V
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G885
Low-power dual function gate
[1] One input at VCC  0.6 V, other inputs at VCC or GND.
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33  VCCV
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.75 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 1.4 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V
[1] -- 75 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G885
Low-power dual function gate
11. Dynamic characteristicsTable 8. Dynamic characteristics
Voltages are referenced to GND (ground=0 V; for test circuit see Figure7.
CL = 5 pF
tpd propagation delay A,Cto 1Y; see Figure6 [2]
VCC = 0.8 V - 17.3 - - - - ns
VCC = 1.1 V to 1.3 V 1.1 5.2 9.7 0.9 12.8 14.2 ns
VCC = 1.4 V to 1.6 V 1.2 3.7 5.9 1.0 7.8 8.6 ns
VCC = 1.65 V to 1.95 V 1.1 3.0 4.8 0.9 6.2 6.9 ns
VCC = 2.3 V to 2.7 V 1.1 2.4 3.6 1.0 4.1 4.5 ns
VCC = 3.0 V to 3.6 V 1.1 2.1 3.1 1.0 3.6 4.1 ns B to 2Y; see Figure6 [2]
VCC = 0.8 V - 21.5 - - - - ns
VCC = 1.1 V to 1.3 V 1.7 6.0 12.7 1.4 12.8 14.2 ns
VCC = 1.4 V to 1.6 V 1.7 4.2 7.2 1.4 7.8 8.7 ns
VCC = 1.65 V to 1.95 V 1.4 3.3 5.8 1.2 6.5 7.2 ns
VCC = 2.3 V to 2.7 V 1.2 2.6 4.1 1.0 4.7 5.2 ns
VCC = 3.0 V to 3.6 V 1.1 2.3 3.5 0.9 3.8 4.2 ns
CL = 10 pF
tpd propagation delay A,Cto 1Y; see Figure6 [2]
VCC = 0.8 V - 20.8 - - - - ns
VCC = 1.1 V to 1.3 V 1.2 6.1 11.4 1.2 14.6 16.1 ns
VCC = 1.4 V to 1.6 V 1.4 4.3 7.2 1.2 8.7 9.6 ns
VCC = 1.65 V to 1.95 V 1.4 3.6 5.7 1.3 6.8 7.5 ns
VCC = 2.3 V to 2.7 V 1.4 2.9 4.2 1.2 4.8 5.4 ns
VCC = 3.0 V to 3.6 V 1.4 2.7 3.9 1.3 4.1 4.6 ns B to 2Y; see Figure6 [2]
VCC = 0.8 V - 25.0 - - - - ns
VCC = 1.1 V to 1.3 V 1.8 6.9 14.4 1.7 14.6 16.1 ns
VCC = 1.4 V to 1.6 V 1.9 4.8 8.5 1.5 9.1 10.1 ns
VCC = 1.65 V to 1.95 V 1.9 3.9 6.6 1.7 7.2 8.0 ns
VCC = 2.3 V to 2.7 V 1.5 3.1 4.7 1.3 5.4 5.9 ns
VCC = 3.0 V to 3.6 V 1.4 2.8 4.3 1.3 4.6 5.1 ns
NXP Semiconductors 74AUP1G885
Low-power dual function gate
CL = 15 pF
tpd propagation delay A,Cto 1Y; see Figure6 [2]
VCC = 0.8 V - 24.3 - - - - ns
VCC = 1.1 V to 1.3 V 1.3 6.9 13.0 1.2 16.2 17.9 ns
VCC = 1.4 V to 1.6 V 1.7 4.9 8.0 1.4 9.7 10.8 ns
VCC = 1.65 V to 1.95 V 1.5 4.1 6.4 1.4 7.6 8.4 ns
VCC = 2.3 V to 2.7 V 1.7 3.4 5.0 1.6 5.4 6.0 ns
VCC = 3.0 V to 3.6 V 1.7 3.1 4.4 1.6 4.7 5.3 ns B to 2Y; see Figure6 [2]
VCC = 0.8 V - 28.5 - - - - ns
VCC = 1.1 V to 1.3 V 2.1 7.7 16.0 1.9 16.3 18.0 ns
VCC = 1.4 V to 1.6 V 2.2 5.4 9.4 2.4 10.3 11.4 ns
VCC = 1.65 V to 1.95 V 2.0 4.4 7.4 1.8 8.2 9.1 ns
VCC = 2.3 V to 2.7 V 1.8 3.6 5.5 1.6 6.0 6.7 ns
VCC = 3.0 V to 3.6 V 1.7 3.3 4.8 1.5 5.2 5.8 ns
CL = 30 pF
tpd propagation delay A,Cto 1Y; see Figure6 [2]
VCC = 0.8 V - 34.7 - - - - ns
VCC = 1.1 V to 1.3 V 2.4 9.2 17.7 2.3 20.9 23.0 ns
VCC = 1.4 V to 1.6 V 2.5 6.5 10.6 2.5 12.2 13.5 ns
VCC = 1.65 V to 1.95 V 2.5 5.4 8.5 2.4 9.4 10.4 ns
VCC = 2.3 V to 2.7 V 2.6 4.5 6.4 2.4 7.0 7.7 ns
VCC = 3.0 V to 3.6 V 2.5 4.2 5.7 2.3 6.6 7.3 ns B to 2Y; see Figure6 [2]
VCC = 0.8 V - 38.9 - - - - ns
VCC = 1.1 V to 1.3 V 2.6 10.0 20.5 2.6 21.5 23.7 ns
VCC = 1.4 V to 1.6 V 2.6 6.9 11.9 2.6 13.2 14.5 ns
VCC = 1.65 V to 1.95 V 2.7 5.7 9.5 2.7 10.5 11.6 ns
VCC = 2.3 V to 2.7 V 2.5 4.7 6.9 2.5 7.6 8.4 ns
VCC = 3.0 V to 3.6 V 2.4 4.4 6.1 2.4 7.1 7.9 ns
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V; for test circuit see Figure7.
NXP Semiconductors 74AUP1G885
Low-power dual function gate
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] All specified values are the average typical values over all stated loads.
[4] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
12. Waveforms
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation
capacitance
fi = 1 MHz; VI= GND to VCC [3][4]
VCC = 0.8 V - 2.7 - - - - pF
VCC = 1.1 V to 1.3 V - 2.9 - - - - pF
VCC = 1.4 V to 1.6 V - 3.0 - - - - pF
VCC = 1.65 V to 1.95 V - 3.1 - - - - pF
VCC = 2.3 V to 2.7 V - 3.5 - - - - pF
VCC = 3.0 V to 3.6 V - 4.1 - - - - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V; for test circuit see Figure7.
Table 9. Measurement points
0.8 V to 3.6 V 0.5  VCC 0.5  VCC VCC  3.0 ns
NXP Semiconductors 74AUP1G885
Low-power dual function gate
[1] For measuring enable and disable times RL = 5 k.
For measuring propagation delays, set-up and hold times and pulse width RL = 1 M.
Table 10. Test data
0.8 V to 3.6 V 5 pF , 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2  VCC

Partno	Mfg	Dc	Qty	Available	Descript
74AUP1G885GM	NXP	N/a	50	avai	Low-power dual function gate