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74ALVT16821DL
20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State
Product specification
Supersedes data of 1997 May 01
IC24 Data Handbook
1998 Feb 13
Philips Semiconductors Product specification
74ALVT168212.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
FEATURES 20-bit positive-edge triggered register 5V I/O Compatible Multiple VCC and GND pins minimize switching noise Live insertion/extraction permitted Power-up reset Power-up 3-State Output capability: +64mA/-32mA Latch-up protection exceeds 500mA per Jedec Std 17 ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTIONThe 74ALVT16821 high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O
compatibility to 5V.
The 74ALVT16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (nOE) controls all ten 3-State buffers
independent of the register operation. When nOE is Low, the data in
the register appears at the outputs. When nOE is High, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
QUICK REFERENCE DATA
ORDERING INFORMATION
Philips Semiconductors Product specification
74ALVT168212.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
PIN CONFIGURATION
Philips Semiconductors Product specification
74ALVT168212.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
PIN DESCRIPTION
FUNCTION TABLE= High voltage level= High voltage level one set-up time prior to the Low-to-High
clock transition= Low voltage level = Low voltage level one set-up time prior to the Low-to-High
clock transition
NC= No change= Don’t care= High impedance “off” state↑= Low to High clock transition= Not a Low-to-High clock transition
LOGIC DIAGRAM
Philips Semiconductors Product specification
74ALVT168212.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74ALVT168212.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE)
NOTES: All typical values are at VCC = 3.3V and Tamb = 25°C. This is the increase in supply current for each input at the specified voltage level other than VCC or GND This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.2V a
transition time of 100μsec is permitted. This parameter is valid for Tamb = 25°C only. Unused pins at VCC or GND. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS (3.3V 0.3V RANGE)GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
Philips Semiconductors Product specification
74ALVT168212.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
AC SETUP REQUIREMENTS (3.3V 0.3V RANGE)GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE)
NOTES: All typical values are at VCC = 2.5V and Tamb = 25°C. This is the increase in supply current for each input at the specified voltage level other than VCC or GND This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ± 0.3V a
transition time of 100μsec is permitted. This parameter is valid for Tamb = 25°C only. Unused pins at VCC or GND. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. Not guaranteed. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
