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74ALVCH32973ZKERPb-freeN/a277avai16-Bit Bus Transceiver and Transparent D-Type Latch with 8 Independent Buffers
74ALVCH32973ZKERTIN/a150avai16-Bit Bus Transceiver and Transparent D-Type Latch with 8 Independent Buffers
74ALVCH32973ZKERPbN/a328avai16-Bit Bus Transceiver and Transparent D-Type Latch with 8 Independent Buffers
SN74ALVCH32973KRTIN/a963avai16-Bit Bus Transceiver and Transparent D-Type Latch with 8 Independent Buffers


SN74ALVCH32973KR ,16-Bit Bus Transceiver and Transparent D-Type Latch with 8 Independent BuffersLOGIC DIAGRAM (POSITIVE LOGIC)A41DIRA31TOEH41LOEH31LEOne of Eight ChannelsC1A61Q11DA11A1A51B1To Sev ..
SN74ALVCH373DW ,Octal Transparent D-Type Latch with 3-State OutputsFEATURESDGV, DW, OR PW PACKAGE• Operates From 1.65 V to 3.6 V(TOP VIEW)• Max t of 3.3 ns at 3.3 Vpd ..
SN74ALVCH373GQNR , OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH373PWR ,Octal Transparent D-Type Latch with 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVCH374 ,Octal Positive-Edge-Triggered D-Type Flip-Flop With 3-State OutputsSCES118G–JULY 1997–REVISED OCTOBER 2004(1)RECOMMENDED OPERATING CONDITIONSMIN MAX UNITV Supply volt ..
SN74ALVCH374PW ,Octal Positive-Edge-Triggered D-Type Flip-Flop With 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74LVC2G07DCKT ,Dual Buffer/Driver with Open-Drain OutputSupport &Product Order Tools &TechnicalCommunityFolder Now Documents SoftwareSN74LVC2G07SCES308L–AU ..
SN74LVC2G07YZPR ,Dual Buffer/Driver with Open-Drain OutputMaximum Ratings . 410 Power Supply Recommendations... 106.2 ESD Ratings........ 411 Layout.... 106. ..
SN74LVC2G08DCTR ,Dual 2-Input Positive-AND Gate SCES198N–APRIL 1999–REVISED DECEMBER 20155 Pin Configuration and FunctionsDCT Package8-Pin SM8Top ..
SN74LVC2G08DCUR ,Dual 2-Input Positive-AND GateSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74LVC2G08SCES198N– ..
SN74LVC2G08DCURG4 ,Dual 2-Input Positive-AND Gate 8-VSSOP -40 to 125Electrical Characteristics....... 612.1 Community Resources...... 126.6 Switching Characteristics.. ..
SN74LVC2G08YZPR ,Dual 2-Input Positive-AND GateLogic Diagram (Positive Logic)– 2000-V Human Body Model (A114-A)11A7– 1000-V Charged-Device Model ( ..


74ALVCH32973ZKER-SN74ALVCH32973KR
16-Bit Bus Transceiver and Transparent D-Type Latch with 8 Independent Buffers
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS

SCES436C–APRIL 2003–REVISED SEPTEMBER 2004 Latch-Up Performance Exceeds 250 mA Per
JESD17
Memberof the Texas Instruments Widebus+™
Family
ESD Protection Exceeds JESD22 Bus Hold on Data Inputs Eliminates the Need – 2000-V Human-Body Model (A114-A)
for External Pullup/Pulldown Resistors – 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)

This device contains eight independent noninverting buffers anda 16-bit noninverting bus transceiver and D-type
latch designed for 1.65-Vto 3.6-V VCC operation.
The SN74ALVCH32973is particularly suitable for demultiplexing an address/data bus intoa dedicated address
bus and dedicated data bus. The deviceis used where thereis asynchronous bidirectional communication
between theA andB data bus, and the address signals are latched and buffered on theQ bus. The theA bus, depending on the logic levelat the direction-control (DIR) input. The transceiver output-enable
(TOE) input can be usedto disable the transceiversso that theA andB buses effectively are isolated.
When the latch-enable (LE) inputis high, theQ outputs follow the data (A) inputs. When LEis taken low, theQ
outputs are latchedat the levels set upat theA inputs. The latch output-enable (LOE) input canbe usedto place
the nineQ outputsin eithera normal logic state (highor low logic level)or the high-impedance state.In the
high-impedance state, theQ outputs neither drive nor load the bus lines significantly. LOE does not affect
internal operationsof the latch. Old data can be retainedor new data can be entered while theQ outputs arein
the high-impedance state. ensure the high-impedance state during power upor power down, LOE and TOE should be tiedto VCC
through pullup resistors; the minimum valuesof the resistors are determinedby the current-sinking capabilityof
the drivers.
The eight independent noninverting buffers perform the Boolean functionY=D and are independentof the state DIR, TOE, LE, and LOE.
TheA andB I/Os andD inputs have bus-hold circuitry. Active bus-hold circuitry holds unusedor undriven data
inputsata valid logic state. Useof pullupor pulldown resistors with the bus-hold circuitryis not recommended.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING

LFBGA- GKE SN74ALVCH32973KR-40°Cto 85°C Tape and reel ACH973LFBGA- ZKE (Pb-free) 74ALVCH32973ZKER
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare availableat
www.ti.com/sc/package.
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