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74ALVCH32374ZKERTIN/a474avai32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85
74ALVCH32374ZKERTEXASINSTRUMN/a1816avai32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85
74ALVCH32374ZKERTI ?N/a464avai32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85


74ALVCH32374ZKER ,32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
74ALVCH32374ZKER ,32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85/sc/package.FUNCTION TABLE(each flip-flop)INPUTSOUTPUTQOE CLK DL ↑ H HL ↑ L LL H or L X Q0H X X ZPl ..
74ALVCH32374ZKER ,32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85FEATURES • Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II• Member of the Texas Instrument ..
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74ALVCH32374ZKER
32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
SN74ALVCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS

SCES283D–OCTOBER 1999–REVISED AUGUST 2004 Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII
Memberof the Texas Instruments Widebus+™
Family
ESD Protection Exceeds JESD22 Operates From 1.65Vto 3.6V – 2000-V Human-Body Model (A114-A) Max tpdof 4.2 nsat 3.3V – 200-V Machine Model (A115-A) ±24-mA Output Driveat 3.3V – 1000-V Charged-Device Model (C101) Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors

This 32-bit edge-triggered D-type flip-flop VCC operation.
The SN74ALVCH32374is particularly registers, I/O ports, bidirectional bus
drivers, and working registers.It canbe used flip-flops,or one 32-bit flip-flop. On
the positive transitionof the clock (CLK) take on the logic levelsat the data
(D) inputs. The output-enable (OE) input outputsin eithera normal logic state
(highor low logic levels)or the high-impedance state.In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and the increased drive provide the capabilityto drive
bus lines without need for interfaceor pullup components. does not affect internal operationsof the flip-flop. Old data canbe retainedor new data canbe entered while
the outputs arein the high-impedance state.
with the bus-hold circuitryis not recommended.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING

LFBGA- GKE SN74ALVCH32374KR-40°Cto 85°C Tape and reel ACH374LFBGA- ZKE (Pb-free) 74ALVCH32374ZKER
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare availableat
www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUTOE CLK D
↑ H H ↑ L L HorL X Q0 X X Z
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