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74ALVCH16500DGGPHIN/a735avai18-bit universal bus transceiver 3-State


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74ALVCH16500DGG
18-bit universal bus transceiver 3-State
Product specification
Supersedes data of 1998 Aug 31
IC24 Data Handbook
1998 Sep 24
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
FEATURES
Complies with JEDEC standard no. 8-1A CMOS low power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V All inputs have bushold circuitry Output drive capability 50Ω transmission lines @ 85°C MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
DESCRIPTION

The 74ALVCH16500 is a high-performance CMOS product.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA)
inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is High. When LEAB is Low, the A data is latched if
CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus
data is stored in the latch/flip-flop on the High-to-Low transition of
CPAB. When OEAB is High, the outputs are active. When OEAB is
Low, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA
and CPBA. The output enables are complimentary (OEAB is active
High, and OEBA is active Low).
To ensure the high impedance state during power up or power
down, OEBA should be tied to VCC through a pullup resistor and
OEAB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf = 2.5ns
NOTES:
CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC 2 × fi +  (CL × VCC 2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;  (CL × VCC 2 × fo) = sum of outputs.
ORDERING INFORMATION
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
PIN CONFIGURATION
PIN DESCRIPTION
BUS HOLD CIRCUIT
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
LOGIC DIAGRAM (one section)
FUNCTION TABLE
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
= High voltage level = High voltage level one set-up time prior to the Enable or Clock transition = Low voltage level = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change = Don’t care = High Impedance ”off” state = High-to-Low Enable or Clock transition
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTE:
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
NOTES:
All typical values are at Tamb = 25°C. Valid for data inputs of bus hold parts.
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