74ALVC164245DGG Fast Delivery |IC PHOENIX CO.,LIMITED

74ALVC164245DGG ,16-bit dual supply translating transceiver 3-StateGeneral descriptionThe 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS dev ..
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74ALVC164245DGG
16-bit dual supply translating transceiver; 3-state
1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables
data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins
nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).
In suspend mode, when one of the supply voltages is zero, there will be no current flow
from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state
and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B)  VCC(A)
(except in suspend mode).
2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range: 3 V port (VCC(A)): 1.5 V to 3.6 V 5 V port (VCC(B)): 1.5 V to 5.5 V CMOS low power consumption Direct interface with TTL levels Control inputs voltage range from 2.7 V to 5.5 V Inputs accept voltages up to 5.5 V High-impedance outputs when VCC(A) or VCC(B) = 0 V Complies with JEDEC standard JESD8-B/JESD36 ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C and 40 C to +125 C
74AL VC164245
16-bit dual supply translating transceiver; 3-state
Rev. 8 — 15 March 2012 Product data sheet
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74ALVC164245DL 40 Cto +125C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74ALVC164245DGG 40 Cto +125C TSSOP48 plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
SOT362-1
74ALVC164245BX 40 Cto +125C HXQFN60 plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4  6  0.5 mm
SOT1134-2
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care; Z= high-impedance OFF-state.
7. Limiting values
Table 2. Pin description
1DIR, 2DIR 1, 24 A30, A13 direction control input
1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, 12 B20, A31, D5, D1, A2, B2, B3, A5 data input/output
2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 A6, B5, B6, A9, D2, D6, A12, B8 data input/output
GND 4, 10, 15, 21, 28, 34, 39, 45 A32, A3, A8, A11, A16, A19, A24, A27 ground (0V)
VCC(B) 7, 18 A1, A10, supply voltage B (5 V bus)
1OE, 2OE 48, 25 A29, A14 output enable input (active LOW)
1A0 to 1A7 47, 46, 44, 43, 41, 40, 38, 37 B18, A28, D8, D4, A25, B16, B15, A22 data input/output
2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 A21, B13, B12, A18, D3, D7, A15, B10 data input/output
VCC(A) 31, 42 A17, A26 supply voltage A (3 V bus)
n.c. - A4, A7, A20, A23, B1, B4, B7, B9, B11,
B14, B17, B19
not connected
Table 3. Function table[1] L nAn = nBn inputs H inputs nBn = nAn Z Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See
[1]
VCC(B) supply voltage B VCC(B) VCC(A) 0.5 +6.0 V
VCC(A) supply voltage A VCC(B) VCC(A) 0.5 +4.6 V
IIK input clamping current VI <0V 50 - mA input voltage [2] 0.5 +6.0 V
VI/O input/output voltage 0.5 VCC +0.5 V
IOK output clamping current VO >VCC or VO <0V - 50 mA output voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.0 V
IO(sink/source) output sink or source
current =0VtoVCC - 50 mA
ICC supply current - 100 mA
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
[2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C
(T)SSOP48 package [3] -500 mW
HXQFN60 package [4]- 1000 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See
[1].
Table 5. Recommended operating conditions
VCC(B) supply voltage B VCC(B) VCC(A)
maximum speed performance 2.7 - 5.5 V
low-voltage applications 1.5 - 5.5 V
VCC(A) supply voltage A VCC(B) VCC(A)
maximum speed performance 2.7 - 3.6 V
low-voltage applications 1.5 - 3.6 V input voltage control inputs: nOE and nDIR 0- 5.5 V
VI/O input/output voltage nAn port 0 - VCC(A) V
nBn port 0 - VCC(B) V output voltage nAn port 0 - VCC(A) V
nBn port 0 - VCC(B) V
Tamb ambient temperature 40 - +125 C
t/V input transition rise
and fall rate
VCC(A)= 2.7Vto 3.0V 0 - 20 ns/V
VCC(A)= 3.0Vto 3.6V 0 - 10 ns/V
VCC(B)= 3.0Vto 4.5V 0 - 20 ns/V
VCC(B)= 4.5Vto 5.5V 0 - 10 ns/V
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
9. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
nBn port
VCC(B) = 3.0 V to 5.5 V [2] 2.0 - - 2.0 - - V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V 2.0 - - 2.0 - - V
VCC(A) = 2.3 V to 2.7 V [2] 1.7 - - 1.7 - - V
VIL LOW-level
input voltage
nBn port
VCC(B) = 4.5 V to 5.5 V [2] -- 0.8 - - 0.8 V
VCC(B) = 3.0 V to 3.6 V [2] -- 0.7 - - 0.7 V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V - - 0.8 - - 0.8 V
VCC(A) = 2.3 V to 2.7 V [2] -- 0.7 - - 0.7 V
VOH HIGH-level
output voltage
nBn port; VI =VIHorVIL= 24 mA; VCC(B) = 4.5 V VCC(B) 0.8 - - VCC(B) 1.2 - - V= 12 mA; VCC(B) = 4.5 V VCC(B) 0.5 - - VCC(B) 0.8 - - V= 18 mA; VCC(B) = 3.0 V VCC(B) 0.8 - - VCC(B) 1.0 - - V= 100 A; VCC(B) = 3.0 V VCC(B) 0.2 VCC(B) -VCC(B) 0.3 VCC(B) -V
nAn port; VI =VIHorVIL= 24 mA; VCC(A) = 3.0 V VCC(A) 0.7 - - VCC(A) 1.0 - - V= 100 A; VCC(A) = 3.0 V VCC(A) 0.2 - - VCC(A) 0.3 - - V= 12 mA; VCC(A) = 2.7 V VCC(A) 0.5 - - VCC(A) 0.8 - - V= 8mA; VCC(A) = 2.3 V VCC(A) 0.6 - - VCC(A) 0.6 - - V= 100 A; VCC(A) = 2.3 V VCC(A) 0.2 VCC(A) -VCC(A) 0.3 VCC(A) -V
VOL LOW-level
output voltage
nBn port; VI =VIHorVIL =24mA; VCC(B) = 4.5 V - - 0.55 - - 0.60V
IO = 12 mA; VCC(B) = 4.5 V - - 0.40 - - 0.80V = 100 A; VCC(B) = 4.5 V - - 0.20 - - 0.30V = 18 mA; VCC(B) = 3.0 V - - 0.55 - - 0.80V = 100 A; VCC(B) = 3.0 V - - 0.20 - - 0.30V
nAn port; VI =VIHorVIL = 24 mA; VCC(A) = 3.0 V - - 0.55 - - 0.80V = 100 A; VCC(A) = 3.0 V - - 0.20 - - 0.30V = 12 mA; VCC(A) = 2.7 V - - 0.40 - - 0.60V = 12 mA; VCC(A) = 2.3 V - - 0.60 - - 0.60V = 100 A; VCC(A) = 2.3 V - - 0.20 - - 0.20V input leakage
current =5.5V orGND - 0.1 5- 0.1 10 A
IOZ OFF-state
output current =VIHor VIL; =VCCor GND
[3] - 0.1 10 - 0.1 20 A
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
[1] All typical values are measured at VCC(B)=5.0 V, VCC(A)=3.3 V and Tamb =25C.
[2] If VCC(A) < 2.7 V, the switching levels at all inputs are not TTL compatible.
[3] For transceivers, the parameter IOZ includes the input leakage current.
[4] VCC(A) = 2.7 V to 3.6 V: other inputs at VCC(A) or GND; VCC(B) = 4.5 V to 5.5 V: other inputs at VCC(B) or GND.
10. Dynamic characteristics
ICC supply current VI =VCCor GND; IO=0A - 0.1 40 - 0.1 80 A
ICC additional
supply current
per control pin; =VCC 0.6 V; IO =0A
[4] - 5 500 - 5 5000 A input
capacitance
-4.0 - - - - pF
CI/O input/output
capacitance
nAn and nBn port - 5.0 - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; for test circuit see Figure7.
tpd propagation
delay
nAn to nBn; see Figure5 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5 3.3 7.6 1.5 9.5 ns
VCC(A) = 2.7 V;
VCC(B)= 4.5 V to 5.5 V
1.0 3.0 5.9 1.0 7.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.0 2.9 5.8 1.0 7.5 ns
nBn to nAn; see Figure5 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.0 3.0 7.6 1.0 9.5 ns
VCC(A) = 2.7 V;
VCC(B)= 4.5 V to 5.5 V
1.0 4.3 6.7 1.0 8.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.2 2.5 5.8 1.2 7.5 ns
NXP Semiconductors 74AL VC164245
16-bit dual supply translating transceiver; 3-state
ten enable time nOE to nBn; see Figure6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5 4.1 11.5 1.5 14.5 ns
VCC(A) = 2.7 V;
VCC(B)= 4.5 V to 5.5 V
1.5 3.6 9.2 1.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.0 3.2 8.9 1.0 12.0 ns
nOE to nAn; see Figure6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.5 4.6 12.3 1.5 15.5 ns
VCC(A) = 2.7 V;
VCC(B)= 4.5 V to 5.5 V
1.5 4.3 9.3 1.5 12.0 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
1.0 3.2 8.9 1.0 11.5 ns
tdis disable time nOE to nBn; see Figure6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
2.0 2.7 10.5 2.0 13.5 ns
VCC(A) = 2.7 V;
VCC(B)= 4.5 V to 5.5 V
2.5 4.6 9.0 2.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
2.1 4.9 8.6 2.1 11.0 ns
nOE to nAn; see Figure6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V
1.0 2.7 9.3 1.0 12.0 ns
VCC(A) = 2.7 V;
VCC(B)= 4.5 V to 5.5 V
1.5 3.5 9.0 1.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V
2.0 3.2 8.6 2.0 11.0 ns
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; for test circuit see Figure7.

Partno	Mfg	Dc	Qty	Available	Descript
74ALVC164245DGG	NXP	N/a	5790	avai	16-bit dual supply translating transceiver 3-State