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Partno	Mfg	Dc	Qty	Available	Descript
74AHC86D	NXP	N/a	2500	avai	Quad 2-input EXCLUSIVE-OR gate
74AHC86PW	NXP	N/a	22500	avai	Quad 2-input EXCLUSIVE-OR gate
74AHCT86D	PH	N/a	102	avai	Quad 2-input EXCLUSIVE-OR gate
74AHCT86D	NXP	N/a	80	avai	Quad 2-input EXCLUSIVE-OR gate
74AHCT86PW	NXP	N/a	75	avai	Quad 2-input EXCLUSIVE-OR gate

74AHC86PW ,Quad 2-input EXCLUSIVE-OR gateLogic diagram (one gate) Fig 3. IEC logic symbol74AHC_AHCT86_2 NXP B.V. 2007. All rights reserved. ..
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74AHCT02PW ,Quad 2-input NOR gate
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74HC374N ,74HC/HCT374; Octal D-type flip-flop; positive edge-trigger; 3-stateGENERAL DESCRIPTIONThe “374” is functionally identical to the “534”, but hasThe 74HC/HCT374 are hig ..
74HC374N.. ,74HC/HCT374; Octal D-type flip-flop; positive edge-trigger; 3-stateGENERAL DESCRIPTIONThe “374” is functionally identical to the “534”, but hasThe 74HC/HCT374 are hig ..
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74AHC86D-74AHC86PW-74AHCT86D-74AHCT86PW
Quad 2-input EXCLUSIVE-OR gate
General descriptionThe 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC
standard no. 7A.
The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function. Features Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than VCC For 74AHC86 only: operates with CMOS input levels For 74AHCT86 only: operates with TTL input levels ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101C exceeds 1000V Multiple package options Speciﬁed from −40 °C to +85 °C and from −40 °C to +125°C Ordering information
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
Rev. 02 — 15 November 2007 Product data sheet
Table 1. Ordering information
74AHC86D −40°Cto +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74AHCT86D
74AHC86PW −40°Cto +125°C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHCT86PW
74AHC86BQ −40°Cto +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quadﬂat package;no leads;14 terminals;
body 2.5×3× 0.85 mm
SOT762-1
74AHCT86BQ
NXP Semiconductors 74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate Functional diagram
NXP Semiconductors 74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate Pinning information
5.1 Pinning
5.2 Pin description Functional description
[1]H= HIGH voltage level;= LOW voltage level.
Table 2. Pin description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8, 11 data outputs
GND 7 ground (0V)
VCC 14 supply voltage
Table 3. Function table[1]
LLL H H
HHL
NXP Semiconductors 74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70°C.
[3] Ptot derates linearly with 5.5 mW/K above 60°C.
[4] Ptot derates linearly with 4.5 mW/K above 60°C. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5V [1] −20 - mA
IOK output clamping current VO< −0.5 V orVO >VCC+ 0.5V [1]- ±20 mA output current VO = −0.5 V to (VCC+ 0.5V) - ±25 mA
ICC supply current - 75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C
SO14 package [2]- 500 mW
TSSOP14 package [3]- 500 mW
DHVQFN14 package [4]- 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 - 5.5 0 - 5.5 V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔV input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V
VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V
NXP Semiconductors 74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate Static characteristics
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
For type 74AHC86
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage
VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage = VIH or VIL= −50 μA; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V= −50 μA; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V= −50 μA; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V= −4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V= −8.0 mA; VCC= 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL = 50 μA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V = 50 μA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V = 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V input leakage
current= 5.5Vor GND; VCC =0V
to 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 2.0 - 20 - 40 μA input
capacitance 3.0 10 - 10 - 10 pF output
capacitance 4.0 - - - - - pF
For type 74AHCT86
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage = VIH or VIL; VCC= 4.5 V= −50μA 4.4 4.5 - 4.4 - 4.4 - V= −8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage = VIH or VIL; VCC= 4.5 V = 50μA - 0 0.1 - 0.1 - 0.1 V = 8.0 mA - - 0.36 - 0.44 - 0.55 V
NXP Semiconductors 74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
10. Dynamic characteristics input leakage
current= 5.5Vor GND; VCC =0V
to 5.5V - 0.1 - 1.0 - 2.0 μA
ICC supply currentVI =VCCor GND; IO = 0 A;
VCC= 5.5V - 2.0 - 20 - 40 μA
ΔICC additional
supply current
per input pin; =VCC− 2.1 V; IO= 0 A;
other pinsat VCC or GND;
VCC= 4.5Vto 5.5V - 1.35 - 1.5 - 1.5 mA input
capacitance 3 10 - 10 - 10 pF output
capacitance 4.0 - - - - - pF
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Figure7.
For type 74AHC86
tpd propagation
delay
nA, nBto nY; see Figure6 [2]
VCC = 3.0 V to 3.6 V=15pF - 4.8 11.0 1.0 13.0 1.0 14.0 ns=50pF - 6.8 14.5 1.0 16.5 1.0 18.5 ns
VCC = 4.5 V to 5.5 V=15pF - 3.4 6.8 1.0 8.0 1.0 8.5 ns=50pF 4.8 8.8 1.0 10.0 1.0 11.0 ns
CPD power
dissipation
capacitance=50 pF; fi = 1 MHz;= GNDto VCC
[3] - 10.0 - - - - - pF
NXP Semiconductors 74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where: = input frequency in MHz, fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
Σ(CL× VCC2×fo)= sum of the outputs.
11. Waveforms
For type 74AHCT86
tpd propagation
delay
nA, nBto nY; see Figure6 [2]
VCC = 4.5 V to 5.5 V=15pF - 3.4 6.9 1.0 8.0 1.0 9.0 ns=50pF - 4.9 8.8 1.0 10.0 1.0 11.0 ns
CPD power
dissipation
capacitance=50 pF; fi = 1 MHz;= GNDto VCC
[3] - 12.0 - - - - - pF
Table 7. Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure7.
Table 8. Measurement points
74AHC86 0.5VCC 0.5VCC
74AHCT86 1.5V 0.5VCC

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