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74AHC74PW -74AHCT74-74AHCT74D
Dual D-type flip-flop with set and reset; positive-edge trigger

Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000V EIA/JESD22-A115-A
exceeds 200V Balanced propagation delays Inputs acceptsvoltageshigher than
VCC For AHC only:
operates with CMOS input levels For AHCT only:
operates with TTL input levels Output capability: standard ICC category: flip-flops Specified from
−40to +85 and +125 °C.
DESCRIPTION

The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs,set (SD) and
reset (RD) inputs; also
complementary Q andQ outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
QUICK REFERENCE DATA

GND=0 V; Tamb =25 °C; tr =tf≤ 3.0 ns.
Notes
CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi+∑ (CL× VCC2×fo) where:= input frequency in MHz; fo= output frequency in MHz; (CL× VCC2×fo)= sum of outputs;= output load capacitance in pF;
VCC= supply voltage in Volts. The condition is VI= GNDto VCC.
FUNCTION TABLES
Table 1
See note1
Table 2
See note1
Note to Tables1 and2
H= HIGH voltage level;= LOW voltage level;= don’t care;= LOW-to-HIGH CP transition;
Qn+1= state after the next LOW-to-HIGH CP transition.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
ORDERING INFORMATION
PINNING
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).
Notes
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
DC CHARACTERISTICS
74AHC family

Over recommended operating conditions; voltage are referenced to GND (ground=0 V).
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
74AHCT family

Over recommended operating conditions; voltage are referenced to GND (ground=0 V).
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
AC CHARACTERISTICS
Type 74AHC74

GND=0 V; tr =tf≤ 3.0 ns.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
Notes
Typical values at VCC= 3.3V. Typical values at VCC= 5.0V.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74AHC74; 74AHCT74
Type 74AHCT74

GND=0 V; tr =tf≤ 3.0 ns.
Note
Typical values at VCC= 5.0V.
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