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74ACTQ74FN/a3avaiQuiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
74ACTQ74FAIN/a123avaiQuiet Series Dual D-Type Positive Edge-Triggered Flip-Flop


74ACTQ74 ,Quiet Series Dual D-Type Positive Edge-Triggered Flip-FlopfeaturesGTOoutputYImproved latch-up immunitycontrol and undershoot corrector in addition to a split ..
74ACTQ74 ,Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
74ACTQ74PC ,Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flopfeatures

74ACTQ74
Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
TL/F/10920
74ACTQ74
Quiet
Series
Dual
D-Type
Positive
Edge-Triggered
Flip-Flop
March 1993
74ACTQ74
Quiet Series Dual D-Type Positive
Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT74isa dual D-type flip-flop with Asynchro-
nous Clear andSet inputs and complementary(Q,Q)out-
puts. Informationatthe inputis transferredtothe outputson
the positive edgeofthe clock pulse. Clock triggering occursa voltage levelofthe clock pulseandisnot directly relat-tothe transition timeofthe positive-going pulse. After
the Clock Pulse input threshold voltagehas been passed,
the Data inputis lockedoutand information presentwillnot transferredto theoutputs untilthe next rising edgeofthe
Clock Pulse input.
The ’ACTQ74 utilizes NSC Quiet Series technologyto guar-
antee quiet output switchingand improved dynamic thresh-
oldperformance. FACTQuiet SeriesTM features GTO output
control and undershoot correctorin additiontoa split
groundbusfor superior performance.
Asynchronous Inputs:
LOW inputtoSD (Set) setsQto HIGH level
LOW inputtoCD (Clear) setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD makes bothQandQ
HIGH
Features ICC reducedby 50% Guaranteed simultaneous switching noise leveland
dynamic threshold performance Guaranteed pin-to-pin skewAC performance Improved latch-up immunity4kV minimum ESD immunity ’ACTQ74has TTL-compatible inputs
Logic Symbols
TL/F/10920–1
IEEE/IEC
TL/F/10920–3
Pin Names Description
D1,D2 Data Inputs
CP1,CP2 Clock Pulse Inputs
CD1,CD2 Direct Clear Inputs
SD1,SD2 DirectSet Inputs
Q1,Q1,Q2,Q2 Outputs
TL/F/10920–2
Connection Diagram
PinAssignment
forDIPand SOIC
TL/F/10920–4
FACTTM,FactQuiet SeriesTM,andGTOTM aretrademarksofNationalSemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
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