74ACTQ657SC ,Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE OutputsFunctional DescriptionThe Transmit/Receive (T/R) input determines the direction select (ODD/EVEN). ..
74ACTQ74 ,Quiet Series Dual D-Type Positive Edge-Triggered Flip-FlopfeaturesGTOoutputYImproved latch-up immunitycontrol and undershoot corrector in addition to a split ..
74ACTQ74 ,Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
74ACTQ74PC ,Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flopfeatures
74ACTQ657SC
Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs
74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs January 1990 Revised September 2000 74ACQ657 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description Features The ACQ/ACTQ657 contains eight non-inverting buffersGuaranteed simultaneous switching noise level and with 3-STATE outputs and an 8-bit parity generator/ dynamic threshold performance checker. Intended for bus oriented applications, the deviceGuaranteed pin-to-pin skew AC performance combines the 245 and the 280 functions in one package. Combines the 245 and the 280 functions in one package The ACQ/ACTQ utilizes Fairchild Quiet Series technol- 300 mil 24-pin slim dual-in-line package ogy to guarantee quiet output switching and improved Outputs source/sink 24 mA dynamic threshold performance. FACT Quiet Series fea- ACTQ has TTL-compatible inputs tures GTO output control and undershoot corrector in addition to a split ground bus or superior performance. Ordering Code: Order Number Package Number Package Description 74ACQ657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ657SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A –A Data Inputs/3-STATE Outputs 0 7 B –B Data Inputs/3-STATE Outputs 0 7 T/R Transmit/Receive Input OE Enable Input PARITY Parity Input/3-STATE Output ODD/EVEN ODD/EVEN Parity Input ERROR Error 3-STATE Output FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of . © 2000 DS010636
