74ACQ374SJ ,Quiet Series Octal D Flip-Flop with 3-STATE OutputsFunctional DescriptionThe ACQ/ACTQ374 consists of eight edge-triggered flip-flops with individual D ..
74ACQ374SJX ,Quiet Series Octal D Flip-Flop with 3-STATE Outputs74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE OutputsJuly 1989Revised Nove ..
74ACQ573 ,Quiet Series Octal Latch with TRI-STATE Outputsfeatures GTO output control andYOutputs source/sink 24 mAundershoot corrector in addition to a spli ..
74ACQ573 ,Quiet Series Octal Latch with TRI-STATE Outputs
74ACQ573PC ,Quiet Series Octal Latch with 3-STATE Outputsfeatures GTO outputeasy interface with microprocessorscontrol and undershoot corrector in addition ..
74ACQ573SJ ,Quiet Series Octal Latch with 3-STATE OutputsFunctional Description Truth TableThe ACQ/ACTQ573 contains eight D-type latches with 3-Inputs Outpu ..
74HC139PW ,74HC/HCT139; Dual 2-to-4 line decoder/demultiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC147D ,74HC/HCT147; 10-to-4 line priority encoderINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC147N ,10-to-4 line priority encoderGENERAL DESCRIPTION• Encodes 10-line decimal to 4-line BCD The 74HC/HCT147 are high-speed Si-gate C ..
74HC148 ,8-3 Line Priority EncoderMM74HC148 8-3 Line Priority EncoderOctober 1987Revised February 1999MM74HC1488-3 Line Priority Enco ..
74HC14D ,74HC/HCT14; Hex inverting Schmitt triggerPin configuration DIP14, SO14 and (T)SSOP14 Fig 5.
74HC14DB ,Hex inverting Schmitt triggerINTEGRATED CIRCUITSDATA SHEET74HC14; 74HCT14Hex inverting Schmitt triggerProduct specification 2003 ..
74ACQ374SJ-74ACQ374SJX-74ACTQ374SC-74ACTQ374SCX
Quiet Series Octal D Flip-Flop with 3-STATE Outputs
74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs July 1989 Revised November 1999 74ACQ374 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACQ/ACTQ374 is a high-speed, low-power octal D-I and I reduced by 50% CC OZ type flip-flop featuring separate D-type inputs for each flip- Guaranteed simultaneous switching noise level and flop and 3-STATE outputs for bus-oriented applications. A dynamic threshold performance buffered Clock (CP) and Output Enable (OE) are common Guaranteed pin-to-pin skew AC performance to all flip-flops. Improved latch-up immunity The ACQ/ACTQ374 utilizes FACT Quiet Series technol- Buffered positive edge-triggered clock ogy to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series fea-3-STATE outputs drive bus lines or buffer memory tures GTO output control and undershoot corrector in address registers addition to a split ground bus for superior performance. Outputs source/sink 24 mA Faster prop delays than the standard AC/ACT374 Ordering Code: Order Number Package Number Package Description 74ACQ374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACQ374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACTQ374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACTQ374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ374QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide 74ACTQ374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description D –D Data Inputs 0 7 CP Clock Pulse Input OE 3-STATE Output Enable Input O –O 3-STATE Outputs 0 7 FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of . © 1999 DS010238
