74ACT16823DLR ,18-Bit Bus-Interface Flip-Flops with 3-State Outputs 54ACT16823, 74ACT16823 18-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS160A – APRIL 1991 – ..
74ACT16825DL ,18-Bit Buffers/Drivers With 3-State Outputs 54ACT16825, 74ACT16825 18-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTSSCAS155B – JANUARY 1991 – REVISED ..
74ACT16841 ,20-Bit Bus-Interface D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
74ACT16841DL ,20-Bit Bus-Interface D-Type Latches With 3-State Outputs 54ACT16841, 74ACT16841 20-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS174A – MAY 1991 ..
74ACT16841DLR , 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
74ACT16863DL ,18-Bit Bus Transceivers With 3-State Outputs 54ACT16863, 74ACT16863 18-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCAS162B – JUNE 1990 – REVISED N ..
74HC174N ,Hex D-type flip-flop with reset; positive-edge triggerPin configuration DIP16 Fig 5.
74HC174PW ,Hex D-type flip-flop with reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC175D ,Quad D-type flip-flop with reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC175DB ,Quad D-type flip-flop with reset; positive-edge triggerGENERAL DESCRIPTIONcorresponding output (Q ) of the flip-flop.nThe 74HC/HCT175 are high-speed Si-ga ..
74HC175N ,Quad D-type flip-flop with reset; positive-edge triggerFeatures and benefits Input levels: For 74HC175: CMOS level For 74HCT175: TTL level Four edge-t ..
74HC175N ,Quad D-type flip-flop with reset; positive-edge triggerapplications where both the truestandard no. 7A.and complement outputs are required and the clock a ..
74ACT16823DLR
18-Bit Bus-Interface Flip-Flops with 3-State Outputs
Parity Flow-Through Architecture Optimizes PCB
Layout Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted
CMOS) 1-μm Process Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
descriptionThese 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, parity bus interfacing, and
working registers.
The ’ACT16823 can be used as two 9-bit flip-flops
or one 18-bit flip-flop. With the clock-enable
(CLKEN) input low, the D-type flip-flops enter data
on the low-to-high transitions of the clock. Taking
CLKEN high disables the clock buffer, thus
latching the outputs. Taking the clear (CLR) input
low causes the Q outputs to go low independently
of the clock.
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74ACT16823 is packaged in theTI shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16823 is characterized for operation over the full military temperature range of 55°C to 125°C. The
74ACT16823 is characterized for operation from –40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
