74ABT374ADB ,Octal D-type flip-flop; positive-edge trigger 3-StatePhilips Semiconductors Product specificationOctal D-type flip-flop; positive-edge trigger74ABT374A( ..
74ABT374AN ,Octal D-type flip-flop; positive-edge trigger 3-StatePIN CONFIGURATION PIN DESCRIPTIONPINSYMBOL FUNCTIONNUMBER1 OE Output enable input (active-Low)OE 1 ..
74ABT374APW ,Octal D-type flip-flop; positive-edge trigger 3-StateFEATURES DESCRIPTIONThe 74ABT374A high-performance BiCMOS device combines low• 8-bit positive edge ..
74ABT374CMSA ,Octal D-Type Flip-Flop with 3-STATE Outputsapplications. A buffered Clock (CP) and Out-
74ABT374AD-74ABT374ADB-74ABT374AN-74ABT374APW
Octal D-type flip-flop; positive-edge trigger 3-State
Philips Semiconductors Product specification
74ABT374AOctal D-type flip-flop; positive-edge trigger
(3-State)
FEATURES 8-bit positive edge triggered register 3-State output buffers Output capability: +64mA/–32mA Latch-up protection exceeds 500mA per Jedec Std 17 ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model Power-up 3-State Power-up reset Live insertion/extraction permitted
DESCRIPTIONThe 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74ABT374AOctal D-type flip-flop; positive-edge trigger
(3-State)
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
FUNCTION TABLE= High voltage level= High voltage level one set-up time prior to the Low-to-High clock transition= Low voltage level = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change= Don’t care= High impedance “off” state= Low-to-High clock transition= not a Low-to-High clock transition
LOGIC DIAGRAM
Philips Semiconductors Product specification
74ABT374AOctal D-type flip-flop; positive-edge trigger
(3-State)
ABSOLUTE MAXIMUM RATINGS1, 2
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74ABT374AOctal D-type flip-flop; positive-edge trigger
(3-State)
DC ELECTRICAL CHARACTERISTICS
NOTES: Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4V. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICSGND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
Philips Semiconductors Product specification
74ABT374AOctal D-type flip-flop; positive-edge trigger
(3-State)
AC SETUP REQUIREMENTSGND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
AC WAVEFORMSVM = 1.5V, VIN = GND to 3.0V
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 2. Data Setup and Hold Times
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Philips Semiconductors Product specification
74ABT374AOctal D-type flip-flop; positive-edge trigger
(3-State)
TEST CIRCUIT AND WAVEFORM
