74ABT16646CMTD ,16-Bit Transceivers and Registers with 3-STATE Outputs74ABT16646 16-Bit Transceivers and Registers with 3-STATE OutputsOctober 1993Revised November 19997 ..
74ABT16646DL ,16-bit bus transceiver/register 3-State
74ABT16646DL ,16-bit bus transceiver/register 3-State
74ABT16652CMTDX ,Octal Transceivers and Registers with 3-STATE Outputs74ABT16652 16-Bit Transceivers and Registers with 3-STATE OutputsApril 1993Revised January 199974AB ..
74ABT16652CSSC ,Octal Transceivers and Registers with 3-STATE OutputsFeaturesThe ABT16652 consists of sixteen bus transceiver circuits Independent registers for A and ..
74ABT16652CSSC ,Octal Transceivers and Registers with 3-STATE Outputs74ABT16652 16-Bit Transceivers and Registers with 3-STATE OutputsApril 1993Revised January 199974AB ..
74F86SJX ,2-Input Exclusive-OR GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74F899 ,9-Bit Latchable Transceiver with Parity Generator/Checkerapplications in place of the74F657 and 74F373 (no need to change T/R to checkparity) Ordering Code: ..
74f899 ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QC ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QCX ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QCX ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74ABT16646CMTD
16-Bit Transceivers and Registers with 3-STATE Outputs
74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs October 1993 Revised November 1999 74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs General Description Features The ABT16646 consists of bus transceiver circuits with 3-Independent registers for A and B buses STATE, D-type flip-flops, and control circuitry arranged forMultiplexed real-time and stored data multiplexed transmission of data directly from the input bus A and B output sink capability of 64 mA, source or from the internal registers. Data on the A or B bus will be capability of 32 mA clocked into the registers as the appropriate clock pin goes Guaranteed latchup protection to a high logic level. Control OE and direction pins are pro- High impedance glitch free bus loading during entire vided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be power up and power down cycle stored in either the A or the B register or in both. The selectNondestructive hot insertion capability controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. Ordering Code: Order Number Package Number Package Description 74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description A –A Data Register A Inputs/ 0 15 3-STATE Outputs B –B Data Register B Inputs/ 0 15 3-STATE Outputs CPAB , CPBA Clock Pulse Inputs n n SAB , SBA Select Inputs n n OE Output Enable Input n DIR Direction Control Input © 1999 DS011644
