54LS138J ,Decoders/DemultiplexersFeaturesused to minimize the effects of system decoding. WhenYDesigned specifically for high speed: ..
54LS138J ,Decoders/Demultiplexersapplications.54LS139) are available. Contact a National Semicon-All of these decoders/demultiplexer ..
54LS139 ,Dual 2-to-4 Line Decoder/Demultiplexerapplications.54LS139) are available. Contact a National Semicon-All of these decoders/demultiplexer ..
54LS139 ,Dual 2-to-4 Line Decoder/Demultiplexer54LS138/DM54LS138/DM74LS138,54LS139/DM54LS139/DM74LS139Decoders/DemultiplexersJune198954LS138/DM54L ..
54LS14 ,Hex Inverter with Schmitt Trigger Inputs54LS14/DM74LS14HexInverterswithSchmittTriggerInputsJune198954LS14/DM74LS14HexInverterswithSchmittTr ..
54LS151 ,8-INPUT MULTIPLEXERSN54/74LS1518-INPUT MULTIPLEXERThe TTL/MSI SN54/74LS151 is a high speed 8-input Digital Multiplexer ..
6TPB100MC , standard products corresponding to the diversification of the needs
6TPB150MC , standard products corresponding to the diversification of the needs
6TPB150MC , standard products corresponding to the diversification of the needs
6TPB150MC , standard products corresponding to the diversification of the needs
6TPB150ML , standard products corresponding to the diversification of the needs
6TPB150ML , standard products corresponding to the diversification of the needs
54LS138J
Decoders/Demultiplexers
TL/F/6391
54LS138/DM54LS138/DM74LS138,
54LS139/DM54LS139/DM74LS139
Decoders/Demultiplexers
June 1989
54LS138/DM54LS138/DM74LS138,
54LS139/DM54LS139/DM74LS139
Decoders/Demultiplexers
General Description
These Schottky-clamped circuitsare designedtobe usedin
high-performance memory-decodingor data-routing appli-
cations, requiring very short propagation delay times.In
high-performance memory systems these decoderscanbe
usedto minimizethe effectsof system decoding. When
used with high-speed memories,the delay timesof these
decodersare usuallyless thanthe typical access time ofthe
memory. This means thatthe effective system delay intro-
ducedbythe decoderis negligible.
The LS138 decodesone-of-eight lines, based uponthe con-
ditionsatthe three binary select inputsand thethreeenable
inputs. Two active-low and one active-high enable inputs
reducethe needfor external gatesor inverters whenex-
panding.A 24-line decodercanbe implemented withnoex-
ternal inverters, anda 32-line decoder requires only one
inverter.An enable inputcanbe usedasa data inputfor
demultiplexing applications.
The LS139 comprisestwo separate two-line-to-four-linede-
codersina singlepackage.The active-low enable inputcan usedasa datalinein demultiplexing applications.
Allof these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized loadtoits driving
circuit.All inputs are clamped with high-performance
Schottkydiodesto suppress line-ringingand simplify system
design.
Features Designed specificallyfor high speed:
Memory decoders
Data transmission systems LS138 3-to-8-line decoders incorporates3 enablein-
putsto simplify cascading and/or data reception LS139 containstwo fully independent 2-to-4-line decod-
ers/demultiplexers Schottky clampedfor high performance Typical propagation delay(3 levelsof logic)
LS13821ns
LS13921ns Typical power dissipation
LS13832 mW
LS13934 mW Alternate Military/Aerospace devices (54LS138,
54LS139)are available. Contacta National Semicon-
ductor Sales Office/Distributorfor specifications.
Connection Diagrams
Dual-in-LinePackage
TL/F/6391–1
Order Number 54LS138DMQB, 54LS138FMQB,
54LS138LMQB, DM54LS138J,DM54LS138W,
DM74LS138Mor DM74LS138N
SeeNS Package Number E20A, J16A,
M16A, N16Eor W16A
Dual-in-Line Package
TL/F/6391–2
Order Number 54LS139DMQB, 54LS139FMQB,
54LS139LMQB, DM54LS139J, DM54LS139W,
DM74LS139Mor DM74LS139N
SeeNS Package Number E20A, J16A,
M16A,N16EorW16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
