54LS112 ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OPFeaturesedge of the clock pulse. Data on the J and K inputs may beYAlternate Military/Aerospace dev ..
54LS112DMQB ,7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset, clear and complementary outputGeneral Description
This device contains two independent negative-edge-trig-
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54LS11DM , TRIPLE 3-INPUT AND GATE
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54LS112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OP
TL/F/6382
54LS112/DM54LS112A/DM74LS112A
Dual
Negative-Edge-Triggered
Master-Slave
J-K
Flip-Flops
with
Preset,
Clear,
and
Complementary
Outputs
June 1989
54LS112/DM54LS112A/DM74LS112A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Preset, Clear,
and Complementary Outputs
General Description
This device containstwo independent negative-edge-trig-
geredJ-K flip-flops with complementary outputs. TheJand datais processedbythe flip-flop onthe falling edge ofthe
clock pulse. The clock triggering occursata voltage level
andisnot directly relatedtothe transition timeofthe falling
edgeofthe clock pulse. DataontheJandK inputs maybe
changed whilethe clockis highorlow without affectingthe
outputsas longasthe setup and hold times arenot
violated.Alow logic levelonthe presetor clear inputswill
setor resetthe outputs regardlessofthe logic levelsofthe
other inputs.
Features Alternate Military/Aerospace device (54LS112)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6382–1
Order Number 54LS112DMQB, 54LS112FMQB,
54LS112LMQB, DM54LS112AJ,DM54LS112AW,
DM74LS112AMor DM74LS112AN
SeeNS Package Number E20A,
J16A, M16A, N16Eor W16A
Function Table
Inputs Outputs CLR CLK J K Q Q X X X H L X X X L H X X X H* H* v LL Q0 Q0 v HL H L v LH L H v H H Toggle H X X Q0 Q0eHigh Logic LeveleLow Logic Levele EitherLoworHigh Logic Levele Negative Going Edgeof PulseeThis configurationis nonstable;thatis,itwillnot persist when preset
and/orclear inputs returntotheir inactive (high) level.eThe outputlogiclevel before theindicatedinput conditionswerees-
tablished.
ToggleeEach output changesto thecomplementofits previous levelon
each fallingedgeofthe clockpulse.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
