54F10 ,Triple 3-Input NAND Gate
54F10 ,Triple 3-Input NAND Gate
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54F109DMQB ,Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-FlopGeneral DescriptionThe F109 consists of two high-speed, completely independent transition clockedJK ..
54F10DM ,Triple 3-Input NAND Gate
54F10DMQB ,Triple 3-Input NAND GateGeneral DescriptionThis device contains four independent gates, each of which performs the logic NA ..
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6AM14 , Silicon N-Channel/P-Channel Power MOS FET Array
6B11 ,Thermocouple Inputs: mV/Volt Inputs: Current Input: Signal Conditioning ModuleGENERAL DESCRIPTION +15mV to +5V as well as 0 to +20mA process current inputs. The 6B11 and 6B11HV ..
6B12 ,Single Channel Signal Conditioning ModuleGENERAL DESCRIPTION the 6B12 and 6B12HV modules for address, input range, baud The 6B12 and 6B12HV ..
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54F10
Triple 3-Input NAND Gate
TL/F/9458
54F/74F10
Triple
3-Input
NAND
Gate
December 1994
54F/74F10
Triple 3-Input NAND Gate
General Description
This device contains three independent gates, eachof
which performsthe logic NAND function.
Commercial Military Package Package DescriptionNumber
74F10PC N14A 14-Lead (0.300× Wide)Molded Dual-In-Line
54F10DM (Note2) J14A 14-Lead CeramicDual-In-Line
74F10SC (Note1) M14A 14-Lead (0.150× Wide)Molded SmallOutline, JEDEC
74F10SJ (Note1) M14D 14-Lead (0.300× Wide)Molded SmallOutline, EIAJ
54F10FM(Note2) W14B 14-Lead Cerpack
54F10LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note1: Devicesalso availablein13×reel.Use suffixeSCXandSJX.
Note2: Militarygrade device withenvironmentaland burn-in processing.Use suffixe DMQB, FMQBand LMQB.
Logic Symbol
IEEE/IEC
TL/F/9458–3
Connection Diagrams
Pin Assignmentfor
DIP,SOICand Flatpak
TL/F/9458–2
Pin Assignment
for LCC
TL/F/9458–1
Unit Loading/Fan Out
54F/74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
An,Bn,Cn Inputs 1.0/1.0 20 mA/b0.6mA Outputs 50/33.3 b1mA/20mA
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C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
