27C2001 Fast Delivery |IC PHOENIX CO.,LIMITED

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27C2001
1 Mbit 128Kb x8 UV EPROM and OTP EPROM
1/16April 1999
M27C2001 Mbit (256Kbx 8) UV EPROM and OTP EPROM 5V± 10% SUPPLY VOLTAGEin READ
OPERATION FAST ACCESS TIME: 55ns LOW POWER CONSUMPTION: Active Current 30mAat 5MHz Standby Current 100μA PROGRAMMING VOLTAGE: 12.75V± 0.25V PROGRAMMING TIME: 100μs/byte (typical) ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 61h
DESCRIPTION
The M27C2001isa high speed2 Mbit EPROMof-
feredinthe two rangesUV (ultra violet erase) and
OTP (one time programmable).Itis ideally suited
for microprocessor systems requiring large pro-
grams andis organisedas 262,144by8 bits.
The FDIP32W (window ceramic frit-seal package)
and LCCC32W (leadless chip carrier package)
havea transparentlids which allowthe usertoex-
posethe chipto ultraviolet lightto erasethebit pat-
tern.A new pattern can thenbe writtento the
deviceby followingthe programming procedure.
For applications wherethe contentis programmed
only one time and erasureis not required, the
M27C2001is offeredin PDIP32, PLCC32 and
TSOP32(8x20 mm) packages.
Figure1. Logic Diagram
AI00716B
A0-A17
Q0-Q7PPVCC
M27C2001
VSS
Table1. Signal Names
A0-A17 Address Inputs
Q0-Q7 Data Outputs Chip Enable Output Enable Program
VPP Program Supply
VCC Supply Voltage
VSS Ground 32
FDIP32W(F) PDIP32(B)
PLCC32(K) TSOP32(N)x20mm
LCCC32W(L)
M27C2001
2/16
Figure2B. LCCPin Connections
AI00718
A17
A10Q2 Q3Q4
A16
A11
A13
A12
M27C2001
A15
A14
Figure2A. DIPPin Connections
A13
A10
A14
A11Q1VSS
A17A16
A12
VPP VCC
A15
AI00717
M27C20018
The operationg modesofthe M27C2001are listedthe Operating Modes table.A single power sup-
plyis requiredinthe read mode.All inputsare TTL
levels exceptfor VPP and 12VonA9for Electronic
Signature.
Read Mode
The M27C2001 has two control functions, bothof
which mustbe logically activein orderto obtain
dataatthe outputs. Chip Enable(E)isthe power
control and shouldbe usedfor device selection.
Output Enable(G)isthe output controland should usedto gate datatothe output pins, indepen-
dentof device selection. Assuming thatthe ad-
dresses are stable, the address access time
(tAVQV)is equalto the delay fromEto output
(tELQV). Datais availableatthe output aftera delay tGLQV fromthe falling edgeofG, assuming that has beenlow andthe addresses have been sta-
bleforat least tAVQV-tGLQV.
Standby Mode
The M27C2001 hasa standby mode which reduc-the supply current from 30mAto 100μA. The
M27C2001is placedinthe standby modebyap-
plyinga CMOS high signaltotheE input. Whenin
the standby mode,the outputsareina high imped-
ance state, independentoftheG input.
Figure2C. TSOPPin Connections A3
A13
A10
A14
A11 G
A17
A16
A12PP
VCC
A15
AI01153B
M27C2001
(Normal) 17SS
3/16
M27C2001
Two Line Output Control
Because EPROMs are usually usedin larger
memory arrays,this product featuresa2line con-
trol function which accommodatesthe useof mul-
tiple memory connection. The two line control
function allows:the lowest possible memory power dissipation, complete assurance that output bus contention
willnot occur.
For the most efficient useof these two control
lines,E shouldbe decoded and usedasthe prima- device selecting function, whileG shouldbe
madea common connectiontoall devicesinthe
array and connectedto the READ line fromthe
system control bus. This ensures thatall deselect- memory devicesarein their lowpower standby
mode and that the output pins are only active
when datais required froma particular memory
device.
Table2. Absolute Maximum Ratings(1)
Note:1. Exceptforthe rating ”Operating Temperature Range”, stressesabove those listedinthe Table ”Absolute Maximum Ratings”may
cause permanent damagetothe device. Theseare stress ratingsonlyand operationofthe device attheseor anyother conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating condi-
tionsfor extended periodsmay affect device reliability. Referalsotothe STMicroelectronics SUREProgram andotherrelevantqual-
ity documents. MinimumDC voltageon Inputor Outputis –0.5Vwith possible undershootto –2.0Vfora periodlessthan 20ns. MaximumDC
voltageon OutputisVCC +0.5Vwith possible overshoottoVCC+2Vfora periodless than20ns. Dependson range.
Table3. Operating Modes
Note:X=VIHor VIL,VID=12V± 0.5V.
Table4. Electronic Signature
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40to125 °C
TBIAS Temperature Under Bias –50to125 °C
TSTG Storage Temperature –65to150 °C
VIO(2) Inputor Output Voltage (exceptA9) –2to7 V
VCC Supply Voltage –2to7 V
VA9(2) A9 Voltage –2to 13.5 V
VPP Program Supply Voltage –2to14 V
Mode E G P A9 VPP Q0-Q7
Read VIL VIL XX VCCorVSS DataOut
Output Disable VIL VIH XX VCCorVSS Hi-Z
Program VIL VIH VIL Pulse X VPP DataIn
Verify VIL VIL VIH XVPP DataOut
Program Inhibit VIH XXX VPP Hi-Z
Standby VIH XXX VCCorVSS Hi-Z
Electronic Signature VIL VIL VIH VID VCC Codes
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’sCode VIL 001 000 00 20h
Device Code VIH 011 000 01 61h
M27C2001
4/16
System Considerations
The power switching characteristicsof Advanced
CMOS EPROMs require careful decouplingofthe
devices. The supply current, ICC, has three seg-
ments thatareof interesttothe system designer:
the standby current level,the active current level,
and transient current peaks thatare producedby
the falling and rising edgesofE. The magnitudeof
the transient current peaksis dependentonthe
capacitive and inductive loadingofthe deviceat
the output.
The associated transient voltage peaks canbe
suppressedby complying withthetwo line output
control andby properly selected decoupling ca-
pacitors.Itis recommended thata 0.1μF ceramic
capacitorbe usedon every device between VCC
and VSS. This shouldbea high frequency capaci-
torof low inherent inductance and shouldbe
placedas closetothe deviceas possible.In addi-
tion,a 4.7μF bulk electrolytic capacitor shouldbe
used between VCC and VSSfor every eight devic-
es. The bulk capacitor shouldbe located nearthe
power supply connection point. The purposeofthe
bulk capacitoristo overcome the voltage drop
causedbythe inductive effectsof PCB traces.
Table5.AC Measurement Conditions
High Speed Standard
Input RiseandFall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0to3V 0.4Vto 2.4V
Inputand Output Timing Ref. Voltages 1.5V 0.8Vand2V
Figure3.AC Testing Input Output Waveform
AI01822
High Speed
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure4.AC Testing Load Circuit
AI01823B
1.3V
OUT= 30pFfor HighSpeed= 100pFfor Standard includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table6. Capacitance(1)(TA =25°C,f=1 MHz)
Note:1. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6pF
COUT Output Capacitance VOUT =0V 12 pF
5/16
M27C2001
Table7. Read ModeDC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V± 5%or5V± 10%; VPP =VCC)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. MaximumDC voltageon OutputisVCC +0.5V.
Table8A. Read ModeAC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V± 5%or5V± 10%; VPP =VCC)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. Sampledonly,not 100% tested.Incaseof45ns speedseeHigh SpeedAC measurament conditions.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤VIN≤VCC ±10 μA
ILO Output Leakage Current 0V≤ VOUT≤ VCC ±10 μA
ICC Supply Current E= VIL,G=VIL,
IOUT= 0mA,f= 5MHz 30 mA
ICC1 Supply Current (Standby)TTL E=VIH 1mA
ICC2 Supply Current (Standby) CMOS E> VCC– 0.2V 100 μA
IPP Program Current VPP =VCC 10 μA
VIL InputLow Voltage –0.3 0.8 V
VIH(2) Input High Voltage 2 VCC+1 V
VOL OutputLow Voltage IOL= 2.1mA 0.4 V
VOH
Output High VoltageTTL IOH= –400μA 2.4 V
Output High Voltage CMOS IOH= –100μAVCC– 0.7V V
Symbol Alt Parameter Test Condition
M27V2001
Unit-55(3) -70 -80 -90
Min Max Min Max Min Max Min Max
tAVQV tACC Address Validto
Output Valid E= VIL,G=VIL 55 70 80 90 ns
tELQV tCE Chip EnableLowto
Output Valid G=VIL 55 70 80 90 ns
tGLQV tOE Output Enable Low Output Valid E=VIL 30 35 40 40 ns
tEHQZ(2) tDF Chip Enable Highto
Output Hi-Z G=VIL 0 30 0 30 0 30 0 30 ns
tGHQZ(2) tDF Output Enable High Output Hi-Z E=VIL 0 30 0 30 0 30 0 30 ns
tAXQX tOH Address Transitionto
Output Transition E= VIL,G=VIL 000 0 ns
M27C2001
6/16
Figure5. Read ModeAC Waveforms
AI00719B
tAXQX
tEHQZ
A0-A17
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Table8B. Read ModeAC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V± 5%or5V± 10%; VPP =VCC)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. Sampledonly,not 100% tested.
Symbol Alt Parameter Test Condition
M27V2001
Unit-10 -12 -15/-20/-25
Min Max Min Max Min Max
tAVQV tACC Address Validto Output
Valid E= VIL,G=VIL 100 120 150 ns
tELQV tCE Chip EnableLowto
Output Valid G=VIL 100 120 150 ns
tGLQV tOE Output Enable Lowto
Output Valid E=VIL 50 50 60 ns
tEHQZ(2) tDF Chip Enable Highto
Output Hi-Z G=VIL 030 0 40050 ns
tGHQZ(2) tDF Output Enable Highto
Output Hi-Z E=VIL 030 0 40050 ns
tAXQX tOH Address Transitionto
Output Transition E= VIL,G=VIL 00 0 ns
Programming
When delivered (and after each erasureforUV
EPROM),all bitsofthe M27C2001 areinthe’1’
state. Datais introducedby selectively program-
ming ’0’s intothe desiredbit locations. Although
only’0’swillbe programmed, both’1’s and’0’scan presentin the data word. The only wayto
changea’0’toa’1’isbydie expositionto ultravio-
let light (UV EPROM). The M27C2001isin the
programming mode when VPP inputisat 12.75V,
EisatVIL andPis pulsedto VIL. The datatobe
programmedis appliedto8 bitsin paralleltothe
data output pins. The levels requiredforthead-
dress and data inputsare TTL. VCCis specifiedto 6.25V ±0.25V.
7/16
M27C2001
Table9. Programming ModeAC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.75V± 0.25V)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP.
Table10. Programming ModeAC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.75V± 0.25V)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0≤VIN≤VIH ±10 μA
ICC Supply Current 50 mA
IPP Program Current E=VIL 50 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC+0.5 V
VOL OutputLow Voltage IOL= 2.1mA 0.4 V
VOH Output High VoltageTTL IOH= –400μA 2.4 V
VID A9 Voltage 11.5 12.5 V
Symbol Alt Parameter Test Condition Min Max Unit
tAVPL tAS Address Validto Program Low 2 μs
tQVPL tDS Input Validto ProgramLow 2 μs
tVPHPL tVPS VPP Highto Program Low 2 μs
tVCHPL tVCS VCC Highto Program Low 2 μs
tELPL tCES Chip EnableLowto ProgramLow 2 μs
tPLPH tPW Program Pulse Width 95 105 μs
tPHQX tDH Program Highto Input Transition 2 μs
tQXGL tOES Input Transitionto Output EnableLow 2 μs
tGLQV tOE Output Enable Lowto Output Valid 100 ns
tGHQZ(2) tDFP Output Enable Highto Output Hi-Z 0 130 ns
tGHAX tAH Output Enable Highto Address
Transition 0ns
M27C2001
8/16
PRESTOII Programming Algorithm
PRESTOII Programming Algorithm allows the
whole arraytobe programmed witha guaranteed
margin,ina typical timeof 26.5 seconds. Pro-
gramming with PRESTOII consistsof applyinga
sequenceof 100μs program pulsesto each byte
untila correct verify occurs (see Figure7). During
programming and verify operation,a MARGIN
MODE circuitis automatically activatedin orderto
guarantee that each cellis programmed with
enough margin.No overprogram pulseis applied
sincethe verifyin MARGIN MODE provides the
necessary marginto each programmed cell.
Program Inhibit
Programmingof multiple M27C2001sin parallel
with different datais also easily accomplished.Ex-
ceptforE,all likeinputs includingGofthe parallel
M27C2001 maybe common.A TTL low level
pulse appliedtoa M27C2001’sP input, withElow
and VPPat 12.75V,will program that M27C2001. high levelE input inhibitsthe other M27C2001s
from being programmed.
Program Verify verify (read) shouldbe performedon the pro-
grammedbitsto determine that they were correct- programmed. The verifyis accomplished withE
andGat VIL,Pat VIH,VPPat 12.75V and VCCat
6.25V.
Figure6. Programming and Verify ModesAC Waveforms
tAVPL
VALID
AI00720
A0-A17
Q0-Q7
VPP
VCC
DATAIN DATAOUT
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM VERIFY
Figure7. Programming Flowchart
AI00715C0
Last
Addr
VERIFY= 100μs Pulse
++n
=25 ++Addr
VCC= 6.25V,VPP= 12.75V
FAIL
CHECKALL BYTES
1st:VCC=6V
2nd:VCC=4.2V
YES
YES
YES

Partno	Mfg	Dc	Qty	Available	Descript
27C2001	ST	N/a	5120	avai	1 Mbit 128Kb x8 UV EPROM and OTP EPROM