100398QC ,Quad Differential ECL/TTL Translating Transceiver with LatchFeaturesThe 100398 is a quad latched transceiver designed to con-
100398QC-100398QI
Quad Differential ECL/TTL Translating Transceiver with Latch
100398 Quad Differential ECL/TTL Translating Transceiver with Latch February 1992 Revised August 2000 100398 Quad Differential ECL/TTL Translating Transceiver with Latch General Description Features The 100398 is a quad latched transceiver designed to con-Differential ECL input/output structure vert TTL logic levels to differential F100K ECL logic levels64 mA FAST TTL outputs and vice versa. This device was designed with the capabil- 25Ω differential ECL outputs with cut-off ity of driving a differential 25Ω ECL load with cutoff capabil- Bi-directional translation ity, and will sink a 64 mA TTL load. The 100398 is ideal for 2000V ESD protection mixed technology applications utilizing either an ECL or TTL backplane.Latched outputs The direction of translation is set by the direction control3-STATE outputs pin (DIR). The DIR pin on the 100398 accepts TTL logic Voltage compensated operating range = −4.2V to −5.7V levels. A TTL LOW on DIR sets up the ECL pins as inputs and TTL pins as outputs. A TTL HIGH on DIR sets up the TTL pins as inputs and ECL pins as outputs. A LOW on the output enable input pin (OE) holds the ECL output in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the latch trans- parent. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-fol- lowers to turn off when the termination supply is −2.0V, pre- senting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100398 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All Inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number Package Description 100398PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100398QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100398QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. FAST is a registered trademark of Fairchild Semiconductor. © 2000 DS010970
