100360QCX , Low Power Dual Parity Checker/GeneratorFeaturesThe 100360 is a dual parity checker/generator. Each half
100360DC-100360QCX
Low Power Dual Parity Checker/Generator
100360 Low Power Dual Parity Checker/Generator March 1998 Revised August 2000 100360 Low Power Dual Parity Checker/Generator General Description Features The 100360 is a dual parity checker/generator. Each halfLower power than 100160 has nine inputs; the output is HIGH when an even number2000V ESD protection of inputs are HIGH. One of the nine inputs (I or I ) has the a b Pin/function compatible with 100160 shorter through-put delay and is therefore preferred as the Voltage compensated operating range = −4.2V to −5.7V expansion input for generating parity for 16 or more bits. Min to Max propagation delay 35% tighter than 100160 The 100360 also has a Compare (C) output which allows the circuit to compare two 8-bit words. The C output isAvailable to industrial grade temperature range LOW when the two words match, bit for bit. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number Package Description 100360PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100360QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100360QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names Description I , I , I , I Data Inputs a b na nb Z , Z Parity Odd Outputs a b C Compare Output Truth Table (Each Half) 28-Pin PLCC Sum of Output HIGH Inputs Z Even HIGH Odd LOW Comparator Function C = (I ⊕ I ) + (I ⊕ I ) + (I ⊕ I ) + (I ⊕ I ) + 0a 1a 2a 3a 4a 5a 6a 7a (I ⊕ I ) + (I ⊕ I ) + (I ⊕ I ) + (I ⊕ I ) 0b 1b 2b 3b 4b 5b 6b 7b © 2000 DS010611
