Z84C20BB6 ,Z80C PIO CMOS VERSIONPin Configuration.
" 20 ll " 23 IL 25 16 JT PB
NC = NO CONNECTION
Another feature of the P ..
Z84C30AB6 ,Z80 CTC CMOS VERSIONapplications. The four inde-
pendently programmable channels of the CTC sat-
isfy common microcom ..
Z84C30BB6 ,Z80 CTC CMOS VERSIONFUNCTIONAL DESCRIPTION
The 2800 CTC has four independent counter/timer
channels. Each channel i ..
Z84C4004PEC , SERIAL INPUT/OUTPUT CONTROLLER
Z84C4008PEC , SERIAL INPUT/OUTPUT CONTROLLER
Z84C4008PEC , SERIAL INPUT/OUTPUT CONTROLLER
Z84C20AB6-Z84C20BB6
Z80C PIO CMOS VERSION
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[iei]fiCF-iC()y'iylz,rEfferiTi(triW((C% 284020
ZBOC PIO CMOS VERSION
n PROVIDES A DIRECT INTERFACE BETWEEN
Z80 MICROCOMPUTER SYSTEMS AND PE-
RIPHERAL DEVICES
n BOTH PORTS HAVE INTERRUPT-DRIVEN
HANDSHAKE FOR FAST RESPONSE
n FOUR PROGRAMMABLE OPERATING
MODES : BYTE INPUT, BYTE OUTPUT, BYTE
" A. V
INPUT/OUTPUT (port A only), AND BIT B D
INPUT/OUTPUT DlP-40 DIP-40
n PROGRAMMABLE INTERRUPTS ON PERIPH- (Plastic) (Ceramic)
ERAL STATUS CONDITIONS
" STANDARD 280 FAMILY BUS-REQUEST AND
PRlORITl2ED INTERRUPT-REQUEST DAISY //\\\ '..
CHAINS IMPLEMENTED WITHOUT EXTER-
NAL LOGIC
I: THE EIGHT PORT B OUTPUTS CAN DRIVE
DARLINGTON TRANSISTORS (1.5 mA at C
1.5 V) PLCC44
a SINGLE 5 V i 10 o/c, POWER SUPPLY (Plastic)
tt LOW POWER CONSUMPTION .' (Ordering Information at the end of the datasheet)
.. 2mAtyp.at4MHz L -
- 3 mA typ. at 6 MHz
- less than 10 “A in Power Down mode
I: EXTENDED OPERATING TEMPERATURE: LOGIC FUNCTIONS
- 40oCTO+85oC
----- Do 50*
""----e 12t .,
DESCRIPTION ------ D, Ar -
DATA H D: As
The 2800 PIO Parallel I/O Circuit is a programm- BUS H m
able, dual-port device that provides a TTL-com- 17:23: CCT-C
patible interface between peripheral devces and ----u, A,
the CPU. The CPU configures the PIO to interface ---- IVAt,rt mm
with awide range of peripheral devices with no other ------ mm" .5”.
external logic. Typical peripheral devices that are mo ...
compatible with the PIO include most keyboards, mmmt - - ff, mm :°
paper tape readers and punches, printers, PROM t
programmers, etc. k
One characteristic of the Z80 peripheral controllers - V01: B,
that separates them from other interface controllers ---- GND a.
PORT A
Gin 3,
' PORT I
is that all data transfer between the peripheral de- Br
vice and the CPU is accomplished under interrupt
control. INTERRUPT (
Thus, the interrupt logic of the PIO permits full use comm
of the efficient interrupt capabilities of the CPU dur-
ing l/O transfers. All logic necessary to implement a
fully nested interrupt structure is included in the PIO.
{in am
H IIllIlII Ht
September 1988 1/14
284C20
Figure1 .' Dual in Line Pin Configuration.
to an,
" u Wi
36 D "fid
" Diai
" D a.
" Cl B,
zuczo 3t Cr"
" Cl s,
" a u,
" Cl n,
26 D Va;
" :1 CLK
" :llEl
22 Creo
21 D anov
ow~aau~puw—
|3303v’
___...._..-
OMOUN‘O
20 2t 22 2] IL 25 26 J",
56119"
NC = NO CONNECTION
Another feature of the PIO is the ability to interrupt
the CPU upon occurrence of specified status condi-
tions in the peripheral device. For example, the PIO
can be programmed to interrupt if any specified pe-
ripheral alarm conditions should occur. This inter-
rupt capability reduces the time the processor must
spend in polling peripheral status,
The 2800 PIO interfaces to peripherals via two in-
dependent general-purpose l/O ports, designated
Port A and Port B. Each port has eight data bits and
two handshake signals, Ready and Strobe, which
2/14 £77 scs-momsom
control data transfer. The Ready output indicates to
the peripheral that the port is ready for a data trans-
fer. Strobe is an input from the peripheral that indi-
cates when a data transfer has occured.
OPERATING MODES
The PIO ports can be programmed to operate in four
modes : byte output (Mode 0), byte input (Mode 1),
byte input/output (Mode 2) and bit input/output
(Mode 3).
In Mode 0, either Port A or Port B can be pro-
grammed to outputdata. Both ports have output reg-
isters that are individually addressed by the CPU ;
data can be written to either port at any time. When
data is written to a port, an active Ready output in-
dicates to the external device that data is available
at the associated port and is ready for transfer to the
external device. After the data transfer, the external
device responds with an active Strobe input, which
generates an interrupt, if enabled.
In Mode 1, either Port A or Port B can be configured
in the input mode. Each port has an input register
addressed by the CPU. When the CPU reads data
from a port, the PIO sets the Ready signal, which is
detected by the external device. The external device
then places data on the l/O lines and strobes the I/O
port, which latches the data into the Port Input Reg-
ister, resets Ready, and triggers the Interrupt Re-
quest, if enabled. The CPU can read the input data
at any time, which again sets Ready.
Mode 2 is bidirectional and uses Port A, plus the in-
terrupts and handshake signals from both ports. "
Port B must be set to Mode 3 and masked off. In
operation, Port A is used for both data input and out-
put. Output operation is similar to Mode 0 except
that data is allowed out onto the Port A bus only
when ASTB is Low. For input, operation is similar to
Mode 1, except that the data input uses the Port B
handshake signals and the Port B interrupt (if en-
abled).
Both ports can be used in Mode 3. In this mode, the
individual bits are defined as either input or output
bits. This provides up to eight separate, individually
defined bits for each port. During operation, Ready
and Strobe are not used. Instead, an interrupt is
generated if the condition of one input changes, or
if all inputs change. The requirements for genera-
ting an interrupt are defined during the programm-
ing operation ;the active level is specified as either
High or Low, and the logic condition is specified as
either one input active (OR) or all inputs active
(AND). For example, if the port is programmed for
active Low inputs and the logic function is AND, then
all inputs at the specified port must go Low to gener-
ate an interrupt.
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