Z8420B ,Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLERK'i'7 SGS-THOMSON
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28420
Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLE ..
Z8420B1 ,Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLERK'i'7 SGS-THOMSON
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28420
Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLE ..
Z8420BB1 ,Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLERK'i'7 SGS-THOMSON
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28420
Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLE ..
Z84C1510AEG , IPC INTELLIGENT PERIPHERAL CONTROLLER
Z84C2006VEC , Provides a direct interface between Z80 microcomputer systems and peripheral devices
Z84C20AB6 ,Z80C PIO CMOS VERSION‘77 StiiS-'rHOMSohll
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Z8420-Z8420AB1-Z8420B-Z8420B1-Z8420BB1
Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLER
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Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLER
u PROVIDES A DIRECT INTERFACE BETWEEN
Z80 MICROCOMPUTER SYSTEMS AND PE-
RIPHERAL DEVICES
" BOTH PORTS HAVE INTERRUPT-DRIVEN
HANDSHAKE FOR FAST RESPONSE
u FOUR PROGRAMMABLE OPERATING
MODES : BYTE INPUT, BYTE OUTPUT, BYTE
INPUT/OUTPUT (Port A only), AND BIT
INPUT/OUTPUT
u PROGRAMMABLE INTERRUPTS ON PERIPH-
ERAL STATUS CONDITIONS
1: STANDARD Z80 FAMILY BUS-REQUEST AND
PRIORITIZED INTERRUPT-REQUEST DAISY
CHAINS IMPLEMENTED WITHOUT EXTER-
NAL LOGIC
" THE EIGHT PORT B OUTPUTS CAN DRIVE
DARLINGTON TRANSISTORS (1.5 mA at
1.5 V)
DESCRIPTION
The Z80 PIO Parallel l/O Circuit is a programmable,
dual-port device that provides a TTL-compatible in-
terface between peripheral devices and the Z80
CPU. The CPU configures the Z80 PIO to interface
with a wide range of peripheral devices with no other
external logic. Typical peripheral devices that are
compatible with the Z80 PIO include most key-
boards, paper tape readers and punches, printers,
PROM programmers, etc.
One characteristic of the Z80 peripheral controllers
that separates them from other interface controllers
is that all data transfer between the peripheral de-
vice and the CPU is accomplished under interrupt
control. Thus, the interrupt logic of the PIO permits
full use of the efficient interrupt capabilities of the
280 CPU during I/O transfers. All logic necessary to
implement a fully nested interrupt structure is in-
cluded in the PIO.
Another feature of the PIO is the ability to interrupt
the CPU upon occurrence of specified status condi-
tions in the peripheral device. For example, the PIO
can be programmed to interrupt if any specified pe-
ripheral alarm conditions should occur. This inter-
rupt capability reduces the time the processor must
spend in polling peripheral status.
The 280 PIO interfaces to peripherals via two inde-
pendent general-purpose l/O ports, designated port
September 1988
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(Ordering Information at the end of the datasheet)
LOGIC FUNCTIONS
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Figure 1 : Dual in Line Pin Configuration.
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A and Port B. Each port has eight data bits and two
handshake signals. Ready and Strobe. which con-
trol data transfer. The Ready output indicates to the
peripheral that the port is ready for a data transfer.
Strobe is an input from the peripheral that indicates
when a data transfer has occured.
OPERATING MODES
The 280 PIO ports can be programmed to operate
in four modes : byte output (mode O), byte input
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(mode 1), byte input/output (mode 2) and bit
input/output (mode 3).
In mode 0. either port A or port B can be pro-
grammed to output data. Both ports have output reg-
isters that are individually addressed by the CPU :
data can be written to either port at any time. When
data is written to a port, an active Ready output in-
dicates to the external dewce that data is available
at the associated port and is ready fortransfer to the
external device. After the data transfer, the external
dewce responds with an active Strobe input, which
generates an interrupt, if enabled.
in mode 1, either port A or port B can be configured
in the input mode. Each port has an input register
addressed by the CPU. When the CPU reads data
from a port. the PIO sets the Ready signal, which is
detected by the external dewce. The external device
then places data on the I/O lines and Strobes the l/O
port, which latches the data into the Port Input Reg-
ister, resets Ready, and triggers the Interrupt Re-
quest, it enabled. The CPU can read the input data
at any time. which again sets Ready.
Mode 2 is bidirectional and uses port A, plus the in-
terrupts and handshake signals from both ports.
Port B must be set to mode 3 and masked off. in
operation. port A IS used for both data input and out-
put. Output operation is similar to mode 0 except
that data is allowed out onto the port A bus only
when ASTB is Low. For input, operation is similar to
mode 1, except that the data input uses the port B.
handshake signals and the port B interrupt (if en-
abled).
Both ports can be used in mode 3. In this mode, the
individual bits are defined as either input or output
bits. This provides up to eight separate, individually
defined bits for each port. During operation, Ready
and Strobe are not used. Instead, an interrupt is
generated it the condition of one input changes, or
if all inputs change. The requirements for genera-
ting an interrupt are defined during the programm-
ing operation ; the active level is specified as either
High or Low, and the logic condition is specified as
either one input active (OR) or all inputs active
(AND). For example, if the port is programmed for
active Low inputs and the logic function is AND, then
all inputs at the specified port mustgo Low to gener-
ate an interrupt.
Data outputs are controlled by the CPU and can be
written or changed at any time.
n Individual bits can be masked off.
a The handshake signals are not used in mode 3.
Ready is held Low, and Strobe is disabled.
I: When using the 280 PIO interrupts, the 280 CPU
interrupt mode must be set to mode 2.
MEERQELL C‘I'itféé
