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WS57C45-25T-WS57C45-35S-WS57C45-35T
HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM
HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM
KEY FEATURES Ultra-Fast Access Time • DESC SMD Nos. 5962-88735/5962-87529— 25 ns Setup
• Pin Compatible with AM27S45 and — 12 ns Clock to Output
CY7C245 Low Power Consumption • Immune to Latch-UP Fast Programming — Up to 200 mA
Programmable Synchronous or • ESD Protection Exceeds 2000 V
Asynchronous Output Enable • Programmable Asynchronous Initialize
Register
GENERAL DESCRIPTIONThe WS57C45 is an extremely High Performance 16K UV Erasable Registered CMOS RPROM. It is a direct
drop-in replacement for such devices as the AM27S45 and CY7C245.
To meet the requirements of systems which execute and fetch instructions simultaneously, an 8-bit parallel data
register has been provided at the output which allows RPROM data to be stored while other data is being
addressed.
An asynchronous initialization feature has been provided which enables a user programmable 2049th word to be
placed on the outputs independent of the system clock. This feature can be used to force an initialize word or
provide a preset or clear function.
A further advantage of the WS57C45 over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This enables the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS57C45 RPROM in a windowed package is 100%
tested with worst case test patterns both before and after assembly.
PIN CONFIGURA TION
PRODUCT SELECTION GUIDE
DC READ CHARACTERISTICS Over Operating Range. (See Above)
AC READ CHARACTERISTICS Over Operating Range. (See Above)
OPERATING RANGE
WS57C45
ABSOLUTE MAXIMUM RATINGS*Storage Temperature............................–65° to + 150°C
Voltage on any Pin with
Respect to Ground ................................–0.6V to +7VPP with Respect to Ground...................–0.6V to + 14V
ESD Protection..................................................>2000V
NOTES:1. CMOS inputs: GND ± 0.3V or VCC± 0.3V. 3. This parameter is only sampled and is not 100% tested. TTL inputs: VIL≤ 0.8V, VIH‡ 2.0V.
CAPACITANCE(4)
WS57C45
TEST LOAD (High Impedance Test Systems)
A.C. TESTING INPUT/OUTPUT WAVEFORM
AC READ TIMING DIAGRAM
BLOCK DIAGRAM
WS57C45
WS57C45
FUNCTION DESCRIPTIONThe WS57C45 is an electrically programmable read only memory produced with WSI’s patented high-performance
self-aligned split gate CMOS EPROM technology. It is organized as 2048 x 8 bits and is pin-for-pin compatible with
bipolar TTL fuse link PROMs. The WS57C45 includes a D-type 8-bit data register on-chip which reduces the
complexity and cost of microprogrammed pipelined systems where PROM data is held temporarily in a register. The
circuit features a programmable synchronous (OES ) or asynchronous (OE) output enable and asynchronous
initialization (INIT).
The programmed state of the enable pin (OES or OE) will dictate the state of gthe outputs at power up. If OES has
been programmed, the outputs will be in the OFF or high impedance state. If OE has been programmed, the
outputs will be OFF or high impedance only if the OE input is HIGH. Data is read by applying the address to inputs10 –A0 and a LOW to the enable input. The data is retrieved and loaded into the master section of the 8-bit data
register during the address set-up time. The data is transferred to the slave output of the data register at the next
LOW to HIGH clock (CP) transition. Then the output buffers present the data on the outputs (O7 –O0).
When using the asynchronous enable (OE), the output buffers may be disabled at any time by switching the enable
input to a logic HIGH. They may be re-enabled by switching the enable to a logic LOW.
When using the sychronous enable (OES ), the outputs revert to a high impedance or OFF state at the next positive
clock edge following the OES input transition to a HIGH state. The output will revert to the active state following a
positive clock edge when the OES input is at a LOW state. The address and synchronous enable inputs are free to
change following a positive clock edge since the output will not change until the next low to high clock transition.
This enables accessing the next data location while previously addressed data is present on the outputs.
To avoid race conditions and simplify system timing, the 8-bit edge triggered data register clock is derived directly
from the system clock.
The WS57C45 has an asynchronous initialize input (INIT). This function can be used during power-up and time-out
periods to implement functions such as a start address or initialized bus control word. The INIT input enables the
contents of a 2049th 8-bit word to be loaded directly into the output data register. The INIT input can be used to
load any 8-bit data pattern into the register since each bit is programmable by the user. When unprogrammed,
activating INIT will result in clearing the register (outputs LOW). When all bits are programmed, actrivating INIT
results in PRESETting the register (outputs HIGH).
When activated LOW, the INIT input results in an immediate load of the 2049th word into both the master and slave
sections of the output register. This is independent of any other input including the clock (CP) input. The initialize
data will be present at the outputs after the asynchronous enable (OE) is taken to a LOW state.
Programming InformationApply power to the WS57C45 for normal read mode operation with CP/PGM, OE/OES and INIT/VPP at VIH . Then
take INIT/VPP to VPP . The part is then in the program inhibit mode operation and the output lines are in a high
impedance state. Refer to Figure 5. As shown in Figure 5, address, program and verify one byte of data. Repeat
this sequence for each location to be programmed.
When intelligent programming is used, the program pulse width is 1 ms in length. Each address location is
programmed and verified until it verifies correctly up to and including 5 times. After the location verifies, an
additional programming pulse should be applied that is X1 times in duration of the sum of the previous programming
pulses before proceeding on to the next address and repeating the process.
Initialization Byte ProgrammingThe WS57C45 has a 2049th byte of data that can be used to initialize the value of the data register. This byte
contains the value “0” when it is shipped from the factory. The user must program the 2049th byte with a value other
than “0” for data register initialization if that value is not desired. Except for the following details, the user may
program the 2049th byte in the same manner as the other 2048 bytes. First, since all 2048 addresses are used up,
a super voltage address feature is used to enable an additional address. The actual address includes VPP on A1and VIL on A2 . Refer to the Mode Selection table. The programming and verification of the Initial Byte is
accomplished operationally by performing an initialize function.
WS57C45
NOTES:5. X = Don’t Care but not to exceed VPP. During read operation, the output latches are loaded on a “0” to “1” transition of CP. During programming and verification, all unspecified pins to be at VIL.
Synchronous Enable ProgrammingThe WS57C45 contains both a synchronous and asynchronous enable feature. The part is delivered configured in
the asynchronous mode and only requires alteration if the synchronous mode is required. This is accomplished by
programming an on-chip EPROM cell. Similar to the Initial Byte, this function is enabled and addressed by using a
super voltage. Referring to the Mode Selection table, VPP is applied to A1 followed by VIH applied to A2 . This
procedure addresses the EPROM cell that programs the synchronous enable feature. The EPROM cell is
programmed with a 10 ms program pulse on CP/PGM. It does not require any data since there is no selection as to
how synchronous enable may be programmed, only if it is to be programmed.
Synchronous Enable VerificationThe WS57C45’s synchronous enable function is verified operationally. Apply power for read operation with OE/OESand INIT/VPP at VIH and take the clock (CP/PGM) from VIL to VIH . The output data bus should be in a high
impedance state. Next take OE/OES to VIL . The outputs will remain in the high impedance state. Take the clock
(CP/PGM) from VIL to VIH and the outputs will now contain the data that is present. Take OE/OES to VIH . The output
should remain driven. Clocking CP/PGM once more from VIL to VIH should place the outputs again in a high
impedance state.
Blank CheckUpon delivery from WaferScale Integration, Inc. or after each erasure (see Erasure section), the WS57C45 has all
2048 bytes in the ‘0’ state. “1’s” are loaded into the WS57C45 through the procedure of programming.
