VV6501C001 ,DUAL-MODE DIGITAL CAMERA CO-PROCESSORelectrical characteristics .....47Chapter 7 Optical Characteristics . . . .487.1 Optical char ..
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VX6953CBQ05I/1 ,5.1 megapixel EDOF camera moduleBlock diagram . . . . 173.2 Digital video block . . 183.2.1 Dark calibration algorithm ..
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VV6501C001
DUAL-MODE DIGITAL CAMERA CO-PROCESSOR
VV6501VGA CMOS Color Image Sensor
Features 640 x 480 VGA resolution 1/4 inch format lens compatible On board 10 bit ADC On board voltage regulators Automatic dark calibration On board audio amplifierI2 C interface Low power suspend mode 4 or 5 wire nibble output Framegrabber signals: QCK and FST
DescriptionThis image sensor based on STMicroelectronics
CMOS technology is Bayer colorised.
The sensor provides a raw digital video output
which also contains embedded codes to facilitate
external synchronisation.
The sensor interfaces to a range of
STMicroelectronics companion processors for
applications such as USB webcams and digital stills
cameras.
An I2 C interface allows an external processor to
configure the device and control exposure and gain
settings.
A low-power pin-driven suspend mode simplifies
USB-based designs.
On board voltage regulators operate from a 5V
USB supply and generate 3V3 and 1V8 power
supplies for external processors.
Technical Specifications
Ordering Details
VV6501
Table of Contents
Chapter 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1 Sensor overview ...................................................................................................................4
1.2 Typical application ................................................................................................................5
Chapter 2 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.1 Pin position ...........................................................................................................................6
2.2 Pin description ......................................................................................................................7
Chapter 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93.1 Video block ...........................................................................................................................9
3.2 Audio block .........................................................................................................................22
3.3 Power management ...........................................................................................................24
3.4 Device operating modes ....................................................................................................26
Chapter 4 Serial Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284.1 General description ............................................................................................................28
4.2 Serial communication protocol ...........................................................................................28
4.3 Types of messages ............................................................................................................30
Chapter 5 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325.1 Register map ......................................................................................................................32
5.2 Register description ...........................................................................................................34
Chapter 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436.1 Absolute maximum ratings .................................................................................................43
6.2 Operating conditions ..........................................................................................................43
6.3 Thermal data ......................................................................................................................43
6.4 DC electrical characteristics ...............................................................................................44
6.5 AC electrical characteristics ...............................................................................................47
Chapter 7 Optical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487.1 Optical characterisation methods .......................................................................................48
7.2 Optical characterisation results ..........................................................................................49
7.3 Spectral response ..............................................................................................................50
7.4 Blooming ............................................................................................................................50
VV6501
Chapter 8 Defect Categorisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518.1 Introduction ........................................................................................................................51
8.2 Pixel defects .......................................................................................................................51
8.3 Sensor array area definition ...............................................................................................52
8.4 Pixel fault definitions ..........................................................................................................53
8.5 Summary pass criteria .......................................................................................................54
8.6 Physical aberrations ...........................................................................................................55
Chapter 9 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 10 Design-In Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5810.1 Basic support circuit ...........................................................................................................58
10.2 Transistor choice ................................................................................................................58
10.3 Pin 1 and image orientation ...............................................................................................58
Chapter 11 Evaluation Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Overview VV6501
1Overview
1.1 Sensor overviewThe VV6501 VGA image sensor produces raw digital video data at up to 30 frames per second. The
image data is digitised using an internal 10-bit column ADC. The resulting 10-bit output data
includes embedded codes for synchronization. The data is formatted as 5-bit nibbles. A separate
data qualification clock (qck) and frame start (fst) signals are also provided.
The sensor is fully configurable using an I2 C interface.
The sensor also contains an audio low-noise preamplifier for use with an external microphone.
The sensor is optimized for USB applications and contains voltage regulators which drive external
pass transistors to produce 3V3 and 1V8 supplies. These supplies may be used by external
processors. A dedicated SUSPEND input pin may be used to force the device into a low power state
while maintaining the device configuration. A power-on reset signal (PORB) may be used to reset
external devices.
Figure 1: VV6501 block diagram
VV6501 Overview
1.2 Typical application
1.2.1 USB webcam This sensor may be used in conjunction with the STMicroelectronics STV0676 co-processor to
produce a low cost USB webcam.
In this application the co-processor supplies the sensor clock and uses the embedded control
sequences to synchronise with the frame and line level timings. It then performs the colour
processing on the raw image data from the sensor before supplying the final image data to the host
using the USB interface.
The voltage regulators on-board the sensor are used to control external bipolar transistors to derive
the supplies for the sensor and co-processor from the 5V USB supply. This approach eliminates the
requirement for more costly external voltage regulation circuitry.
Figure 2 below illustrates a typical system using VV6501.
The input USB supply is 5V . The 3V3 digital regulator generates the supply for the sensor digital
part and the co-processor IOs. The 1V8 regulator generates the core supply for the co-processor.
Figure 2: USB camera system using STV0676
Device Pinout VV6501 Device Pinout
2.1 Pin position
Figure 3: Pin position
VV6501 Device Pinout
2.2 Pin description
Table 1: Pin description
Device Pinout VV6501
Table 1: Pin description
VV6501 Functional Description Functional DescriptionThe first three sections of this chapter detail the main blocks in the device: Video Audio Power management
The final section describes the device level operating modes including suspend.
3.1 Video block
3.1.1 OverviewThe analog core of the video block contains a VGA sized pixel array. The integration time and
access for a row of pixels is controlled by the Y -address block. The row of pixels being read is
converted using a 10-bit in-column ADC. The digitised data is readout into the digital block for
formatting. The 10-b data is transferred to the co-processor over a 5-wire digital bus as two 5-b
nibbles.
The exposure or integration time for the pixel array is calculated by the external co-processor and
delivered to the sensor using the I2C interface.
Data synchronization can be achieved either by using the embedded codes within the data stream
or by making use of the dedicated FST and QCK pins.
Figure 4: Overview of video block
Functional Description VV6501
3.1.2 Imaging arrayThe physical pixel array is 656 x 496 pixels. The pixel size is 5.6 μm by 5.6 μm.
The additional border columns and rows are included to enable complete color reconstruction of the
final 640 by 480 sized array.
MicrolensMicrolenses placed above the visible pixels improve light gathering capability hence improving
sensitivity.
3.1.3 Sensor data overviewSensor data is output on a 5-wire bus. As well as pixel data there are embedded codes at the start
and end of every video line. These codes are always preceded by an escape sequence which is
guaranteed not to appear in the video data itself.
Figure 5: Pixel array
Table 2: Video data values
VV6501 Functional Description
3.1.4 Digital data bus: D[4:0]Sensor data may be either 8 or 10 bits per pixel and is transmitted as follows:
10-bit data: A pair of 5-bit nibbles, most significant nibble first, on 5 wires. 8-bit data: A pair of 4-bit nibbles, most significant nibble first, on 4 wires.In 5-wire mode, the embedded control codes occupy only the most significant 8-bits, the least
significant 2-bits are always zero.
Output tri-state using SIFRegister 23 bit[5] can be used to tri-state all 5 data lines, QCK and FST.
Output pad drive strengthThe data and QCK output pads are tri-stateable with 4 mA drive.
3.1.5 Data qualification clock (QCK)A data qualification clock (QCK) is available and complements the embedded control sequences.
This clock runs continuously when enabled and consists of:
Fast QCK: the falling edge of the clock qualifies every 5 or 4-bit data blocks that constitute a pixel value.
Slow QCK: the rising edge qualifies 1st, 3rd, 5th, etc. blocks of data that constitute a pixel value while the falling edge qualifies the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire
mode, the rising edge of the clock qualifies the most significant nibbles while the falling edge of
the clock qualifies the least significant nibbles.
Figure 6: Digital data output modes
Figure 7: QCK modes
Functional Description VV6501
3.1.6 Line formatsEach line of data from the sensor starts with an escape sequence followed by a line code that
identifies the line type. The line code is then followed by two bytes that contain a coded line number.
Each line is terminated with an end-of-line code followed by a line average. The one exception to
this is the first line in the frame where the end of line code is followed by a frame count.
The line code formats are detailed in Figure9.
Figure 8: Line data format
VV6501 Functional DescriptionThe line code absolute value depends on whether 5-wire or 4-wire output mode has been selected,
as shown in Table3.
Figure 9: Line code format
Table 3: Line codes
Functional Description VV6501
Start of frame line format The start of frame line contains the contents of the first 16 serial interface registers rather than any
video data. This information immediately follows the line code at the beginning of the line. The code H is output after each serial interface value.
It takes 32 pixel clock periods to output these 16 serial interface register values. The remaining pixel
periods of the video portion of the line are padded out using 07H values. The first two pixel locations
are also padded with 07H characters (Figure 10). If a serial interface register location is unused then
the value from register 0 is output.
Following the escape sequence and line code at the end of active video, a frame count is output.
Active video line formatAll video data is contained on active video lines. The pixel data appears as a continuous stream of
bytes within the active lines.
Black line formatThe black lines contain information from the sensor black lines (held in zero exposure). This
information may be used by certain co-processors.
Dark line formatThe dark lines contain information from the sensor dark lines (shielded from light by metal). The
information from these lines is used by the sensor to calculate a dark average offset value which is
then applied to the video data to ensure a known ‘black’ level for image data.
Blank line format o reduce the frame rate it is possible to extend the frame length by adding blank data lines. These
contain no video or black line data. In default VGA mode there are no blank lines.
End of frame line formatThe end of frame line sole purpose is to indicate the end of a frame, it contains no video data.
Figure 10: Start of frame line format
VV6501 Functional Description
Line DurationTable 4 shows the image duration and interline intervals with default setup.
Extending line lengthsThe user can extend the line length by writing to serial registers 82 and 83. The line length padding
is inserted after the EAV sequence, ensuring that the distance between the SAV and EAV
sequences remains constant.
3.1.7 Frame formatEach video frame is composed of a sequence of data lines as illustrated in Figure 11.
Extending the inter-frame periodThe user may choose to extend the inter-frame period by increasing the frame length by writing to
serial registers 97 and 98. In this event, the appropriate number of additional blank lines is inserted
between the End Of Frame (EOF) line and the Start Of Frame (SOF) line. This means that the
distance between SOF and EOF remains constant.
Table 4: Line timing
Figure 11: VGA frame format
Functional Description VV6501
Timing of Frame Start signal (FST) The frame-level position of FST is illustrated in Figure 12.
The FST pulse qualifies the Status Line information and is 648 QCKs (slow) long.
Figure 12: FST timing overview
Figure 13: Detailed FST timing
VV6501 Functional Description
3.1.8 Image translationsThe imaging array can be readout with different modes as described here below: Shuffle horizontal readout, bit [7] of serial register [17]. Even columns (2,4,6.) are readout first. Mirror horizontal readout, bit [3] of serial register [22]. Columns are readout in reverse order. Mirror vertical readout, enabled by setting [4] of serial register [22]. Rows are readout in
reverse order.
Figure 14: Image readout modes
Functional Description VV6501
3.1.9 Dark calibrationIn order to produce a high quality output image from the VV6501, it is necessary to accurately
control the black level of the video signal. There are two main sources of error: Dark current Offsets in the output path.
The black level is corrected by using dark pixel rows to “learn” the offset so that it can then be
subtracted from the image data. Dark rows have the same exposure setting as the visible lines but
are shielded from incident light.
For 10-b data the ideal “black” code is set to be 64 (when viewing 8-b data the ‘black’ code should
be 16). The aim of the dark calibration algorithm is to “learn” the offset required such that “black”
image lines have code 64.
Figure 15: Overview of dark offset cancellation
Figure 16: Role of dark offset calibration
VV6501 Functional Description
Dark calibration algorithmThe dark line monitoring logic accumulates a number of dark pixels, calculates an average and then
compares this average with the appropriate black level. There is a bit in serial register 45 which
determines whether the offset applied is the user-programmable value from serial register 44, or the
value calculated by the offset cancellation processor.
The dark offset cancellation algorithm accumulates data from the dark lines which is input to a leaky
integrator and an appropriate offset is calculated.
Following an exposure/gain change, on power up or when going out of suspend mode, the history in
the dark calibration leaky integrator is reset to the incoming value as the previously stored value will
be out of date.
User controlThe serial interface allows the user the following additional controls: Accumulate dark pixels, calculate dark pixel average and report, but do not apply anything to
data stream Accumulate dark pixels, calculate dark pixel average, report and apply internally calculated
offset to data stream Accumulate dark pixels, calculate dark pixel average and report, but apply a SIF supplied offset
3.1.10 Sensor clock and frame rate controlThe frame rate is determined by both the input sensor clock and some additional registers under
user control.
Sensor clockThe sensor requires a single-ended clock input. A 24MHz clock is required to generate 30 frames
per second VGA images. The results is a pixel rate of 12MHz.
Slower frame ratesIn order to achieve slower frame-rates the user has a number of options: increase the inter-frame time by adding blank line (via SIF register) apply a slower external clock divide down the external clock using the sensor internal clock divider (via SIF register)
Clock dividerThe sensor contains a 4-bit register with which the user selects the clock divider setting (N). Table5
gives the mapping between the clk_div value and the divider ratio.
Table 5: User programmable clock divider values
Functional Description VV6501
3.1.11 Exposure/gain controlThe sensor does not contain any form of automatic exposure or gain control. T o produce a correctly
exposed image, exposure and gain values must be calculated externally and written to the sensor
via the serial interface.
Exposure calculationThe exposure time for a pixel and the ADC range (therefore the gain) are programmable via the
serial interface. The explanation below assumes that the gain and exposure values are updated
together as part of a 5 byte serial interface auto-increment sequence.
Exposure time combines coarse, fine exposure, pixel rate also related to frame and line lengths, all
defined in Table6.
Example of exposure calculation in default VGA video modecoarse exposure = 522
fine exposure = 762
Input clock frequency - Fclkin = 24MHz,
Pixel period = 2/(24 x 106 ) = 8.33 x10-8 s
Calculation: exposure time = 8.33 x10-8 x [(522 x 762) +762] = 33.2 ms
Table 6: Definitions related to exposure
Table 5: User programmable clock divider values
VV6501 Functional DescriptionThe available range of exposure (without using clock division) is shown in Table7.
3.1.12 Gain timing and exposure updatesExposure and gain values are re-timed within the sensor to ensure that a new set of values is only
applied to the sensor array at the start of each frame. Bit 0 of the status register is set high when a
new exposure value is written via the serial interface but has not yet been applied to the sensor
array.
There is a 1 frame latency between a new exposure value being applied to the sensor array and the
results of the new exposure value being read-out. The same latency does not exist for the gain
value. To ensure that the new exposure and gain values are aligned up correctly the sensor delays
the application of the new gain value by one frame relative to the application of the new exposure
value. o eliminate the possibility of the sensor array seeing only part of the new exposure and gain
settings, if the serial interface communication extends over a frame boundary, the internal re-timing
of exposure and gain data is disabled while writing data to any location in the exposure page of the
serial interface register map. Thus, if the 5 bytes of exposure and gain data is sent as an auto-
increment sequence, it is not possible for the sensor to consume only part of the new exposure and
gain data.
Table 7: Exposure ranges [24MHz system clock]
Functional Description VV6501
3.2 Audio blockThe audio amplifier is designed to drive an external ADC, possibly in the co-processor, with an
amplified audio signal taken from a FET microphone input. The 3-bit gain control and power down
for the reference are controlled via the I2 C interface.
3.2.1 Co-processor support for audioTable 8 below summarizes the audio capability of the different co-processors the VV6501 is
intended to work with.
Figure 17: VV6501 audio amplifier overview
Table 8: Co-processor support for audio
VV6501 Functional Description
3.2.2 Audio amplifier key features Very high PSRR micro bias reference due to bandgap from the 3.3V regulated supply, as well
as RC network for LF filtering in the audio bandwidth. Fully differential low-noise amplifier with gain control via serial IF (0dB to +42dB in 6dB steps).
Up to 1.8Vpp dynamic range on AUDOUTP and AUDOUTN
Figure 18: VV6501 audio amplifier in typical application
Functional Description VV6501
3.3 Power management
3.3.1 Voltage regulatorsThe power management block on the device avoids the requirement for any external system
regulators in a 5 V based camera product. The scheme is shown in Figure 19. Digital Regulator 1 - This 5 V to 3.3 V regulator uses an external bipolar transistor to supply
loads up to 200 mA. It is typically used to power the sensor digital logic and may also be used
to supply an external co-processor if required. This regulator is always on. Digital Regulator2 - This 3.3 V to 1.8 V regulator uses an external bipolar transistor to supply
loads up to 100 mA. This supply may be used for an external co-processor if required. This
regulator is controlled by the PDREG1V8 pin and must be switched off if not required. Audio Amp Regulator - This 5 V to 3.3 V regulator supplies the audio amplifier and the buffer
amplifier used to supply the reference to the microphone (Load 5 mA). It should be externally
decoupled with a 2.2 μF capacitor. For applications without audio this regulator may be
powered down via the SIF registers. Video Regulator - This 5 V to 3.3 V regulator supplies the analogue video circuitry. It should be
externally decoupled with a 2.2 μF capacitor.
Figure 19: Voltage regulator block diagram
VV6501 Functional Description
3.3.2 Power-on reset cellThe power-on reset cell generates a low going pulse whenever the digital power supplies are below
their lower limits. The power-on reset signal resets the sensor internally and is also available on the
PORB pin and may be used to reset a co-processor.
The PORB cell monitors both the 3V3 and 1V8 supplies. If the 1V8 supply is not required then
PDVREG1V8 must be tied high.
Figure 20: Power-on reset block
Functional Description VV6501
3.4 Device operating modes
3.4.1 Power-upOn power up the sensor is in low-power mode. All data bus lines drive high to indicate that the
device is “present”.
3.4.2 Waking up the sensor The sensor is made to exit low power mode by enabling the external clock and writing to SIF
register16 bit 0. The first frame output after exiting low-power mode does not contain any valid video
data.
3.4.3 Low power modeEntering low-power mode during video streaming causes the analogue circuits to be powered
down. The values of the serial interface registers is preserved.
Figure 21: Exiting low-power mode
VV6501 Functional Description
3.4.4 Suspend modeSuspend mode is the lowest possible power consumption mode with current < 100 μA. In suspend
mode the external clock is gated inside the device and the analogue blocks are powered down.
The sensor is set into suspend mode by driving the SUSPEND pin high. o achieve the lowest possible power consumption, the clock source should also be turned OFF for
the duration of the SUSPEND mode.
3.4.5 Sensor soft resetAll the serial interface registers may be reset to their default values by setting the “soft reset” bit (bit
2) of setup register 0. This causes the sensor to enter low power mode.
Serial Control Bus VV6501 Serial Control Bus
4.1 General descriptionThe 2-wire I2C serial interface bus is used to read and write the sensor control registers.
Some status registers are read-only.
The main features of the serial interface include: Variable length read/write messages. Indexed addressing of information source or destination within the sensor. Automatic update of the index after a read or write message. Message abort with negative acknowledge from the master. Byte oriented messages.
4.2 Serial communication protocolThe co-processor must perform the role of communication ‘master’ and the sensor acts as a ‘slave’.
The communication from host to sensor takes the form of 8-bit data with a maximum serial clock
frequency of 100 kHz. Since the serial clock is generated by the bus master it determines the data
transfer rate. Data transfer protocol on the bus is illustrated in Figure 22.
4.2.1 Data formatInformation is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The internal
data is produced by sampling sda at a rising edge of scl. The external data must be stable during
the high period of scl. Exceptions to this are start (S) or stop (P) conditions when sda falls or rises
respectively, while scl is high.
A message contains at least two bytes preceded by a start condition and followed by either a stop or
repeated start, (Sr) followed by another message.
Figure 22: Serial Interface data transfer protocol
VV6501 Serial Control BusThe first byte contains the device address byte which includes the data direction read, (r), ~write,
(~w), bit.
The byte following the address byte contains the address of the first data byte (also referred to as
the index). The serial interface can address up to 128 byte registers. If the MSB of the second byte
is set, the automatic increment feature of the address index is selected.
4.2.2 Message interpretationAll serial interface communications with the sensor must begin with a start condition. If the start
condition is followed by a valid address byte then further communications can take place. The
sensor will acknowledge the receipt of a valid address by driving the sda wire low. The state of the
read/~write bit (LSB of the address byte) is stored and the next byte of data, sampled from sda, can
be interpreted.
During a write sequence the second byte received is an address index and is used to point to one of
the internal registers. The MSB of the following byte is the index auto increment flag. If this flag is
set then the serial interface will automatically increment the index address by one location after
each slave acknowledge. The master can therefore send data bytes continuously to the slave until
the slave fails to provide an acknowledge or the master terminates the write communication with a
stop condition or sends a repeated start, (Sr). If the auto increment feature is used the master does
not have to send indexes to accompany the data bytes.
As data is received by the slave, it is written bit by bit to a serial/parallel register. After each data byte
has been received by the slave, an acknowledge is generated, the data is then stored in the internal
register addressed by the current index.
During a read message, the current index is read out in the byte following the device address byte.
The next byte read from the slave device are the contents of the register addressed by the current
index. The contents of this register are then parallel loaded into the serial/parallel register and
clocked out of the device by scl.
At the end of each byte, in both read and write message sequences, an acknowledge is issued by
the receiving device. Although VV6501 is always considered to be a slave device, it acts as a
Figure 23: VV6501 Serial interface address
Figure 24: Serial interface data format
Serial Control Bus VV6501At the end of a sequence of incremental reads or writes, the terminal index value in the register will
be one greater than the last location read from or written to. A subsequent read will use this index to
begin retrieving data from the internal registers.
A message can only be terminated by the bus master, either by issuing a stop condition, a repeated
start condition or by a negative acknowledge after reading a complete byte during a read operation.
4.3 Types of messagesThis section gives guidelines on the basic operations to read data from and write data to the serial
interface.
The serial interface supports variable length messages. A message may contain no data bytes, one
data byte or many data bytes. This data can be written to or read from common or different locations
within the sensor. The range of instructions available are detailed below. Write no data byte, only sets the index for a subsequent read message. Multiple location write (using auto increment index bit) for fast information transfers.
Examples of these operations are given below. A full description of the internal registers is given in
the previous section. For all examples, the slave address used is 3210 for writing and 3310 for
reading. The write address includes the read/write bit (the LSB) set to zero while this bit is set in the
read address.
4.3.1 Single location, single data writeWhen a random value is written to the sensor, the message looks as shown in Figure 25.
In this example, the fineH exposure register (index = 3210 ) is set to 8510 . The r/w bit is set to zero for
writing and the Inc. bit (MSB of the index byte) is set to zero to disable automatic increment of the
index after writing the value. The address index is preserved and may be used by a subsequent
read. The write message is terminated with a stop condition from the master.
4.3.2 Single location, single data readA read message always contains the index used to get the first byte.
Figure 25: Single location, single write
Figure 26: Single location, single read
