VV6404C001 ,CIF resolution colour digital CMOS image sensorGeneral Description . . . 275.2 Serial Communication Protocol . .275.3 Data Format ..
VV6404C001 ,CIF resolution colour digital CMOS image sensorGeneral description . . . . .94.2 Embedded control data . .94.2.1 The combined escape and ..
VV6410 ,Mono and Colour Digital Video CMOS Image Sensorsfeatures already available in the successful STV0680B-001 chipset, Audio Record And Playbackincludi ..
VV6410C036 ,DUAL-MODE DIGITAL CAMERA CHIPSETfeatures included in STV0680B-003 ● STV0680B-003 fully backward compatible allow audio memos to be ..
VV6411C036 ,DUAL-MODE DIGITAL CAMERA CHIPSETTable of contentsChapter 1 Introduction . . . . . .61.1 Digital camera chipset .......61.2 C ..
VV6444C001 ,Low Cost Digital Camera (LCDC) ChipsetFEATURES• CIF (352 x 288) or VGA (640 x 480) resolution sensorSTMicroelectronics (ST), Imaging Divi ..
WSD411 , Surface Mount Schottky Barrier Diode
WSD411 , Surface Mount Schottky Barrier Diode
WSD520G , Surface Mount Schottky Barrier Diodes
WSD520S , Surface Mount Schottky Barrier Diodes
WSD551H , SMALL SIGNAL SCHOTTKY DIODES 500m AMPERES 30 VOLTS
WSD551H , SMALL SIGNAL SCHOTTKY DIODES 500m AMPERES 30 VOLTS
VV6404C001
Mono and Colour Digital Video CMOS Image Sensors
Mono and Colour Digital Video CMOS Image Sensors
VV5404 & VV6404
DESCRIPTIONVV5404 and VV6404 are highly integrated CMOS VLSI
sensors which enables high standards of performance and
image quality at a very cost-effective price point. The 356 x
292 monochrome device offers one of the simplest routes
currently available to design-in of imaging applications, while
the colour device is ideal for low cost PC camera applications.
Both devices incorporate a comprehensive range of on-board
controls eliminating the need for additional support chips. On-
chip A/D conversion provides 8 bit digital output and the
device set up is fully automatic via the built-in automatic black
level calibration algorithm.
Exposure and gain settings are programmable and operation
is controlled via a serial interface.
This sensors offer variable frame rates of up to 30 frames per
second and a 4 wire digital video bus. The digital interface
also provides a tri-stateable data qualification clock and frame
synchronisation signal.
Hand-held products, in applications such as PDAs, bar code
scanning or automatic meter reading, will benefit from the low
power requirements and from the inbuilt sleep and power
down modes.
The price and performance standards introduced with the
VV5404 and VV6404 enable use of an imaging solution
where previously it may not have been practicable on cost
grounds.
BLOCK DIAGRAM
FEATURES CIF Format mono or colour pixel array Up to 30 frames per second operation On-chip 8 bit analogue to digital converter Low power consumption Up to 356 x 292 pixel image size Automatic exposure and gain control Serial interface control Programmable exposure and gain values Automatic black level calibration 4-wire digital video bus Evaluation kit available
APPLICATIONS PC Cameras Biometrics Inspection Systems
SPECIFICATIONS
Important: A colour co-processor is required to convert the VV6404 sensor’s video
data stream of raw colourised pixel data into either a CIF or QCIF for-
mat RGB or YUV colour image. VV5404 and VV6404 do NOT have any form of automatic exposure
control. This must be performed externally.
SDA
SCL
D[3:0]
CLKO
OEB
FST
QCK
SIN
CLKI
VV5404 & VV6404
Table of Contents
1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.1 Image Read-out Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2 Frame Rate Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3. Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Digital Video Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94.1 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Embedded control data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2.1 The combined escape and sync character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2.2 The command word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2.3 Supplementary Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3 Video timing reference and status/configuration data. . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3.1 Blank lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.2 Black line timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3.3 Valid video line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.4 Start of frame line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.5 End of frame line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.4 Detection of sensor using data bus state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.5 Resetting the Sensor Via the Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Power-up, Low-power and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.6.1 Power-Up/Down (Figure 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6.2 Low-Power Mode (Figure 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.6.3 Sleep Mode (Figure 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.6.4 Application of the system clock during sensor low-power modes . . . . . . . . . . . . . . . 22
4.7 Qualification of Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7.1 Using the External Clock signal applied to CKI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7.2 Data Qualification Clock, QCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.7.3 Frame Start Signal, FST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5. Serial Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Serial Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.3 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.4 Message Interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.5 The Programmers Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.5.1 DeviceH [000_00002] and DeviceL [000_ 00012] . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5.2 Status0 [000_00102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.5.3 Line_count_H [000_00112] & Line_count_L [000_01002]. . . . . . . . . . . . . . . . . . . . .31
5.5.4 Setup0 [001_00002] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.5.5 Setup1 [001_00012] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.5.6 Setup2 [001_00102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.5.7 Setup4 [001_01002] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.5.8 Setup5 [001_01012] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.5.9 Exposure Control Registers [010_00002] - [010_10012]. . . . . . . . . . . . . . . . . . . . . . 35
5.5.10 ADC Setup Register AS0 [111_01112] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.6 Types of messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6.1 Single location, single data write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
VV5404 & VV64045.6.2 Single location, single data read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.6.3 No data write followed by same location read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6.4 Same location multiple data write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6.5 Same location multiple data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6.6 Multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6.7 Multiple location read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
5.7 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6. Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426.8 Synchronising 2 or More Cameras . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
7. Detailed specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
7.2 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8. Physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468.1 Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8.3 48LCC Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8.4 VV6404 Sensor Support Circuit Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.5 Sensor Support Circuit Component List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
VV5404 & VV6404 IntroductionVV5404 and VV6404 are CIF format CMOS image sensors capable of outputing digital pixel data at frame rates, of
upto 30 frames per second. The VV5404 is a monochrome part, while the VV6404 has a colour filter applied over the
sensor array.
Important: The VV6404 sensor’s video data stream only contains raw colourised pixel data. A colour co-processor is required to generate for example either a CIF or a QCIF format YUV colour image.
The 356 x 292 pixel sensors have an on-chip 8-bit analogue to digital converter (Figure 1). The sensors offer very
flexible digital interface, the main components of which are listed below: A tri-stateable 4-wire data bus (D[3:0]) for sending both video data and embedded timing references. A data qualification clock, QCK, which can be programmable via the serial interface to behave in a number of
different ways (Tri-stateable). A frame start signal, FST (Tri-stateable). A 2-wire serial interface (SDA,SCL) for controlling and setting up the device. The ability to synchronise the operation of multiple cameras - synchronisation input, SIN.
An 8-bit pixel value is transmitted across the 4 wire tri-stateable databus as series pair of 4-bit nibbles, most significant
nibble first. Along within the pixel data, codes representing the start and end frames and the start and end of lines are
embedded within the video data stream to allow the video processor to synchronise with video data the camera
module is generating. Section 4. defines the format for the output video datastream.
To complement the embedded control sequences a data qualification clock, QCK, and a frame start signal are also
available. QCK can be set-up to either be: Disabled Free-running. Qualify only the control sequences and the pixel data. Qualify the pixel data only
There is also the choice of two different QCK frequencies, where one is twice the frequency of the other.
SDA
SCL
D[3:0]
CLKO
Figure 1 : Block Diagram of VV5404 and VV6404 Image SensorsOEB
FST
QCK
SIN
CLKI
VV5404 & VV6404 Fast QCK: the falling edge of the clock qualifies the nibble data irrespective of whether it is the most or the least
significant nibble. Slow QCK: the rising edge of the clock qualifies the most significant nibbles while the falling edge of the clock
qualifies the least significant nibbles.
The FST can be enabled/disabled via the serial interface.
OEB tri-states all 4 databus lines, D[3:0], the qualification clock, QCK and the frame start signal, FST.
There are 3 main ways of interfacing to the VV5404 or VV6404 sensor based on the above signals: The processor capturing the data (or colour co-processor for VV6404) supplies the sensor clock, CKI, and uses
the embedded control sequences to synchronise with the frame and line level timings. Thus the processor and
sensor are running off derivatives of the same fundamental clock (4 fsc - 14.31818 MHz). To allow the receiver
to determine the best sampling position of the video data, during its power-up sequence the sensor outputs a
101010... sequence on each of its databus lines for the video processor to lock on to. The video processor uses a free-running QCK supplied by the sensor to sample the incoming video data
stream. The embedded control sequences are used to synchronise the frame and line level timings. A crystal is
used to generate the clock for the sensor. The video processor uses FST and the data only mode for QCK to synchronise to the incoming video data. Pri-
marily intended for interfacing to frame grabbers.
The 2-wire serial interface provides complete control over how the sensor is setup and run. Exposure and gain values
are programmed via this interface. Section 5. defines the communications protocol and the register map of all the
locations which can be accessed via the serial interface.
Using the first two interface options outlined above it is possible to control the sensor and receive video data via a 9-
wire cable between the sensor and the video processor/colour-processor. A 4-wire data bus (D[3:0]) for sending both video data and embedded timing references. A 2-wire serial interface (SDA,SCL). The clock for the sensor or QCK from the sensor. VCC and GND power lines.
The various image read-out and frame rate options are detailed in Sections 2 and 3 respectively.
Figure 2 : Interfacing OptionsSDA
SCL
D[3:0]
CLKI
SDA
SCL
D[3:0]
QCKFST
VV5404 & VV6404 Operating Modes
2.1 Image Read-out OptionsThe output image format is CIF (352 x 288 pixel array). To provide the colour co-processor with the extra information
it needs for interpolation at the edges of the VV6404 pixel array, an optional border 2 pixels deep on all 4 sides of the
array can be enabled (Figure 4). The resulting image size of 356 x 292 pixels is the default power up state for this
camera module. The border option is programmable via the serial interface.
Image read-out is either non-interlaced raster scan, or ‘shuffled’ non-interlaced raster scan.
The shuffled raster scan order differs from a conventional raster in that the pixels of individual rows are re-ordered,
with the odd pixels within a row read-out first, followed by the even pixels.
This ‘shuffled’ read-out within a line, is useful in the VV6404 device as it groups pixels of the same colour (according
to the Bayer pattern - Figure 3) together, reducing cross talk between the colour channels.
NOTE: This option is on by default in both VV5404 and VV6404 sensors and is controllable via the serial interface.
2.2 Frame Rate OptionsTwo options: 30 fps or 25 fps (Assuming a 7.15909 MHz input clock and the default clock divider setting). The number
of video lines in for each frame rate is the same (304), the slower frame rate is implemented by extending the line
period from 393 pixel periods to 471 pixel periods. 30 fps is the default option, the frame rate is programmable via the
serial interface.
Table 1 : Image Format Selection.
Table 2 : Frame Rate SelectionEven
Columns
(0, 2, 4,...)
Odd
Columns
(1, 3, 5,...)
Even
Rows
(0, 2, 4,...)
Odd
Rows
(1, 3, 5,...)
Figure 3 : Bayer Colourisation Pattern. (VV6404 only)
VV5404 & VV6404289 291290 320
Figure
4
: V
louris
ed Im
For92 Pi
xel
Pi
2,
3,
. 35
2,
3, 3
0, 1, 2, 3,... ... 288, 289, 290, 291
Borde
and Columns
l Arra
VV5404 & VV6404 Exposure ControlThe exposure time for a pixel and the gain of the input amplifier to the 8-bit ADC are programmable via the serial
interface. The explanation below assumes that the gain and exposure values are updated together as part of a 5 byte
serial interface auto-increment sequence.
The exposure is divided into 2 components - coarse and fine. The coarse exposure value sets the number of lines a
pixel exposes for, while the fine exposure sets the number of additional pixel clock cycles a pixel integrates for. The
sum of the two gives the overall exposure time for the pixel array.
30 fps mode: Exposure Time = (Clock Divisor) x (Coarse x 393 + Fine) x (CKI clock period)/
25 fps mode: Exposure Time = (Clock Divisor) x (Coarse x 471 + Fine) x (CKI clock period)
If an exposure value is loaded outwith the valid ranges listed in the above table the value is clipped to lie within the
above ranges.
Exposure and gain values are re-timed within the sensor to ensure that a new set of values is only applied to the
sensor array at the start of each frame. Bit 0 of the Status Register is set high when a new exposure value is written
via the serial interface but has not yet been applied to the sensor array.
There is a 1 frame latency between a new exposure value being applied to the sensor array and the results of the
new exposure value being read-out. The same latency does not exist for the gain value. To ensure that the new
exposure and gain values are aligned up correctly the sensor delays the application of the new gain value by one
frame relative to the application of the new exposure value.
To eliminate the possibility of the sensor array seeing only part of the new exposure and gain setting, if the serial
interface communications extends over a frame boundary, the internal re-timing of exposure and gain data is disabled
while writing data to any location in the Exposure page of the serial interface register map. Thus if the 5 bytes of
exposure and gain data is sent as an auto-increment sequence, it is not possible for the sensor to consume only part
of the new exposure and gain data.
Table 3 : Coarse and Fine Exposure Ranges.
Table 4 : Main Gain Steps.
VV5404 & VV6404 Digital Video Interface Format
4.1 General descriptionThe video interface consists of a unidirectional, tri-stateable 4-wire databus. The nibble transmission is synchronised
to the rising edge of the system clock (Figure 13).
Digital video data is 8 bits per sample, transmitted as serial pairs of parallel 4-bit nibbles (most significant nibble first)
on 4 wires.
Multiplexed with the sampled pixel data is control information including both video timing references and sensor
status/configuration data. Video timing reference information takes the form of field start characters, line start
characters, end of line characters and a line counter.
Where hexadecimal values are used, they are indicated by a subscript H, such as FFH ; other values are decimal.
4.2 Embedded control dataTo distinguish the control data from the sampled video data all control data is encapsulated in embedded control
sequences. These are a minimum of 6 words long and includes a combined escape/sync character, 1 control word
(the ‘command byte’) and 2 words of supplementary data.
To minimise the susceptibility of the embedded control data to random bit errors redundant coding techniques have
been used to allow single bit errors in the embedded control words to be corrected. However, more serious corruption
of control words or the corruption of escape/sync characters cannot be tolerated without loss of sync to the data
stream. To ensure that a loss of sync is detected a simple set of rules has been devised. The four exceptions to the
rules are outlined below: Data containing a command words that has two bit errors. Data containing two ‘end of line’ codes that are not separated by a ‘start of line’ code. Data preceding an ‘end of frame’ code before a start of frame’ code has been received. Data containing line that do not have sequential line numbers (excluding the ‘end of frame’ line).
If the video processor detects one of these violations then it should abandon the current frame of video.
4.2.1 The combined escape and sync characterEach embedded control sequence begins with a combined escape and sync character that is made up of three words.
The first two of these are FFH FFH - constituting two words that are illegal in normal data. The next word is 00H -
guaranteeing a clear signal transition that allows a video processor to determine the position of the word boundaries
in the serial stream of nibbles. Combined escape and sync characters are always followed by a command word -
making up the four word minimum embedded control sequence.
4.2.2 The command wordThe word that follows the combined escape/sync characters defines the type of embedded control data. Three of the
8 bits are used to carry the control information, four are ‘parity bits’ that allow the video processor to detect and correct
a certain level of errors in the transmission of the command words, the remaining bit is always set to 1 to ensure that
the command word is never has the value 00H . The coding scheme used allows the correction of single bit errors (in
the 8-bit sequence) and the detection of 2 bit errors. The three data bits of the command word are interpreted as
shown in Figure 5.
Table 5 : Video encoding parameters
VV5404 & VV6404
Figure 5
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VV5404 & VV6404
Figure 7 :
Line Dat
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8 E
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93 P
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Pi
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ne
Sta
of F
e (
End
of F
e (
ng
Lev
P = Va
lid
Bl
k Pi
l D
P = Va
lid
Pi
l D
ens
atus
Da
ng
Lev
VV5404 & VV6404The even parity bits are based on the following relationships: An even number of ones in the 4-bit sequence (C2, C1, C0 and P0). An even number of ones in the 3-bit sequence (C2, C1, P1). An even number of ones in the 3-bit sequence (C2, C0, P2). An even number of ones in the 3-bit sequence (C1, C0, P3).
Table 6 shows how the parity bits maybe used to detect and correct 1-bit errors and detect 2-bit errors.
4.2.3 Supplementary DataThe last 2 bytes of the embedded control sequence contains supplementary data. This normally contains the current
line number except if the line code is the end of line, the 2 bytes are padded out using null characters (FFH ). The 12
bit line number is packaged up by splitting it into two 6-bit values. Each 6-bit values is then converted into an 8-bit
value by adding a zero to the start and an odd word parity bit at the end.
4.3 Video timing reference and status/configuration dataThe video sequence is made up of lines of data. Each field of data is constructed of the following data lines: A start of frame line 2 of ‘black lines’ (used for black level calibration) 7 (9) of blank lines 292 (288) active video lines An end of frame line 1 (3) blank lines
The numbers given in () are for when the border rows and columns are not output on the databus.
Each line of data starts with an embedded control sequence that identifies the line type (as outlined in Table 3). The
control sequence is then followed by two bytes that, except in the case of the end-of-frame line, contain a coded line
number. The line number sequences starts with the start-of-frame line at 00H and increments one per line up until the
end-of-frame line. Each line is terminated with an end-of-line embedded control sequence. The line start embedded
sequences must be used to recognise data lines as a number of null bytes may be inserted between data lines.
Table 6 : Detection of 1-bit and 2-bit errors in the Command Word
VV5404 & VV6404
4.3.1 Blank linesIn addition to padding between data lines, actual blank data lines may appear in the positions indicated above. These
lines begin with start-of-blank-line embedded control sequences and are constructed identically to active video lines
except that they will contain only blank bytes (07H).
4.3.2 Black line timingThe black lines (which are used for black level calibration) are identical in structure to valid video lines except that
they begin with a start-of-black line sequence and contain either information from the sensor ‘black lines’ or blank
bytes (07H).
4.3.3 Valid video line timingAll valid video data is contained on active video lines. The pixel data appears as a continuous stream of bytes within
the active lines. The pixel data may be separated from the line header and end-of-line control sequence by a number
of ‘blank’ bytes (07H ), e.g. when the border lines and pixels are disabled 07H is output in place of pixels 0, 1, 354 and
4.3.4 Start of frame line timing
The start of frame line which begins each video field contains no video data but instead contains the contents of all
the serial interface registers. This information follows the start-of-line header immediately and is terminated by an
end-of-line control sequence. To ensure that no escape/sync characters appear in the sensor status/configuration
information the code 07H is output after each serial interface value. Thus it takes 256 pixel clock periods (512 system
clocks) to output all 128 of the serial interface registers. The remainder of the 356 pixel periods of the video portion
of the line is padded out using 07H values. The first two pixel locations are also padded with 07H characters (Figure 8)
If a serial interface register location is unused then 07H is output. The read-out order of the registers is independent
of whether the pixel read-out order is shuffled or un-shuffled.
4.3.5 End of frame line timingThe end of frame line which begins each video field contains no video data. Its sole purpose is to indicate the end of
a frame.
4.4 Detection of sensor using data bus stateThe video processor device must have internal pull-down terminations on the data bus. On power-up a sensor will
pull all data lines high for a guaranteed period. This scheme allows the presence of a sensor on the interface to be
detected by the video processor on power-up, and the connection of a sensor to an already power-up interface (a
‘hot’ connection).
The absence of a sensor is detected by the video processor seeing more than 32 consecutive nibbles of 0H on the
data bus. On detecting the absence of a sensor, CKI, should be disabled (held low).
The presence of a sensor is detected by the video processor seeing more than 32 consecutive nibbles of FH on the
data bus. On detecting the presence of a sensor, CKI, should be enabled.
4.5 Resetting the Sensor Via the Serial InterfaceBit 2 of setup register 0 allows the VV6404 sensor to be reset to its power-on state via the 2-wire serial interface.
Setting this “Soft Reset” bit causes all of the serial interface registers including the “Soft Reset” bit to be reset to their
default values. This “Soft Reset” leaves the sensor in low-power mode and thus an “Exit Low-Power Mode” command
(Section 4.6.2) must be issued via the serial interface before the sensor will start to generate video data (Figure 9).
4.6 Power-up, Low-power and Sleep modesTo clarify the state of the interface on power-up and in the case of a ‘hot’ connection of the interface cable the power-
up state of the bus is defined below.
VV5404 & VV6404
Figure
8 : S
us Line Data Format.
Da
s, D[t of
Li
ne C
ode
Numb
er 0
Dev
egi
0)
(Re
r 1
ddi
ter
VV5404 & VV6404
Figure
9
: R
ing t
VV6
4 S
nsor
via
e S
ria
Int3:0]
mbe
p0[
p0[
VV5404 & VV6404
Table 7 : System Power-Up or Hot-plugging Device Behaviour
VV5404 & VV6404
4.6.1 Power-Up/Down (Figure 12) On power-up all of the databus lines will go high Immediately (FH ), to indicate that the device is “present” and the
device enters it low-power mode (Section 4.6.2).
When the Video Processor is reset the following sequence should be executed to ensure that the VM6404 starts to
generate video data: After the Video Processor has been released from reset, the sensor clock, CLKI, should be enabled immedi-
ately After waiting for at least 16 CLKI clock cycles, a “Soft Reset” command should be issued to the sensor. This is
necessary to ensure that the sensor is brought into a known state. If the sensor is not present then the serial
interface communications by Video Processor will not be acknowledged. Poll for 32 consecutive FH values on the data bus, if this condition is satisfied then the sensor is present. The
Video processor should set the camera_present flag. Determine if the serial CMOS E2 PROM containing the defectivity map for the sensor is present and down-load
the values. Disable the sensor clock CKI. The Video Processor should generate the VP_Ready interrupt. Once the host software serviced the VP_Ready interrupt, then the sensor and video processor is ready to gen-
erate video data. To enable video data, the host software, sets the low-power mode bit low. The video processor must enable
CLKI at least 16 CLKI clock cycles before issuing the “Exit Low-Power Mode” command via the serial interface.
After the “Exit Low-Power Mode” command has been sent the sensor will output for one frame, a continuous stream
of alternating 9H and 6H values on D[3:0]. By locking onto the resulting 0101/1010 patterns appearing on the data bus
lines the video processor can determine the best sampling position for the nibble data. After the last 9H 6H pair has
been output the databus returns to FH until the start of fifth frame after CKI has been enabled when the first active
frame output. After the video processor has determined the correct sampling position for the data, it should then wait
for the next start of frame line (SOF).
If the video processor detects 32 consecutive 0H values on the data bus, then the sensor has been removed. The
sensor clock, CKI, should be held low.
4.6.2 Low-Power Mode (Figure 10)Under the control of the serial interface the sensor analogue circuitry can be powered down and then be powered up.
When the low-power bit is set via the serial interface, all the databus lines will go high at the end of the end of frame
line of the current frame. At this point the analogue circuits in the sensor will power down. The system clock must
remain active for the duration of low power mode.
Only the analogue circuits are powered down, the values of the serial interface registers e.g. exposure and gain are
preserved.
The internal frame timing is reset to the start of a video frame on exiting low-power mode.
In a similar manner to the previous section, the first frame after the serial comms contains a continuous stream of
alternating 9H and 6H to allow the video processor to re-confirm its sampling position. Then three frames latter the
first start of frame line is generated.
4.6.3 Sleep Mode (Figure 11)Sleep mode is similar to the low-power mode, except that analogue circuitry remains powered. When the sleep
command is received via the serial interface the pixel array will be put into reset and the data lines all will go high at
the end of the current frame. Again the system clock must remain active for the duration of sleep mode.
When sleep mode is disabled, the CMOS sensor’s frame timing is reset to the start of a frame. During the first frame
after exiting from sleep mode the databus will remain high, while the exposure value propagates through the pixel
array. At the start of the second frame the first start of field line will be generated.
VV5404 & VV6404
Figure 10 : Entering
and Exiting Lo
w P
wer Modep0[
VV5404 & VV6404
Figure
11
ring
and
Exi
Sleep
Mode3:0]
mbe
p0[1
VV5404 & VV6404
Figure 12 : System P
Up or Hot-plug
ing De
vice Beha
viour 0V
Reg
ted
Pow
D[3
:0]
CLK
Fra
Num
ber
de
eady
Cam
a_P
tup
[2]
tup
[0]
VV5404 & VV6404
4.6.4 Application of the system clock during sensor low-power modesFor successfully entry and exit into and out of low power and ‘sleep’ modes the system clock, CLKI, must remain
active for the duration of these modes.
4.7 Qualification of Output DataThere are two distinct ways for qualifying the data nibbles appearing of the output data bus
4.7.1 Using the External Clock signal applied to CKIThe data on the output data bus, changes on the rising edge of CKI. The delay between the video processor supplying
a rising clock edge and the data on the databus becoming valid, depends on the length of the cable between the
sensor and the video processor. To allow the video processor to find the best sampling position for the data nibbles,
via the serial interface the databus can be forced to output continuously 9H, 6H, 9H, 6H,...
4.7.2 Data Qualification Clock, QCKVV6404 provides a data qualification clock for the output bus. There are two frequencies for the qualification clock:
one runs at the nibble rate and the other at the pixel read-out rate. The falling edge of the fast QCK qualifies every
nibble irrespective of whether it is most or least significant nibble. For the slow QCK, the rising edge qualifies the most
significant nibbles in the output data stream and the falling edge qualifies the least significant nibbles in the output
data stream.
There are 4 modes of operation of QCK. Disabled (Always low - (Default) Free running - qualifies the whole of the output data stream. Embedded control sequences, status data and pixel data. Pixel Data Only.
The operating mode for QCK is set via the serial interface. The QCK output is tristated when OEB is high.In one of
the modes available via the serial interface the slow version of QCK will appear on the QCK pin while the fast version
of the same signal will appear on the FST pin.
In the case where the border rows and columns are disabled, there is simply no qualification pulse at that point in time
i.e. when pixels 0,1, 354 and 355 are normally output.
The QCK pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor
to control external devices, e.g. stepper motors, shutter mechanisms. The configuration details for QCK can be found
in sections 5.5.7 and 5.5.8 of this document.
4.7.3 Frame Start Signal, FSTThere are 3 modes of operation for the FST pin programmable via the serial interface: Disabled (Always Low- Default). Frame start signal. The FST signal occurs once frame, is high for 356 pixel periods (712 system clock periods)
and qualifies the data in the start of frame line.
The FST is tristated when OEB is high.
The FST pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor
to control external devices, e.g. stepper motors, shutter mechanisms.
The configuration details for FST can be found in sections 5.5.7 and 5.5.8 of this document.
VV5404 & VV6404l D
13 : Qualification of Output
ta (Bor
der Ro
ws and Columns
Enab
d).
Line
For
wir
Nibb
Ou
tput M
ode
- D
l Cloc
or
l c
loc
pplie
d to CKI
cat
Clo
k, Q
) Fr
run
(ii) Contr
que
Da
l D= P
l V
e -
Mo
Si
gni
fic
Ni
bbl
e, P
Val
Lea
st
gni
fic
t Ni
bbl
e, P
8-
t Pi
Val
ast
ali
cat
Clo
(i) Fr
unning
(ii) Contr
l s
que
nd Pix
Da
Pi
VV5404 & VV64042 B
lac
Li
nes
Bl
ank
ine
s (
Vi
e L
ine
s (
t of I
e (
Num
ber
Lin
Figure
14 :
Frame Le
vel Ti
mings f
FST and
QCK (B
der
ws and Colum
s Enab
led)ame
Pe
04
Lin
d of
Ima
ge (
FST
QCK
ame
Format
r rows
columns
ena
d -
Def
VV5404 & VV6404
Figure
15
Frame Le
vel Tim
ngs f
FST an
QCK (
der Ro
ws and Columns Disab
ed)FST
QCK
e Dat
2 Bl
ine
s (
9 B
Lin
Vi
e Li
s (
Sta
t of I
e (
Pe
iod
04 L
ine
d of
Imag
e (
Fra
e Forma
t (Borde
r r
and c
lumns dis
bled
) :Lin
Numb
VV5404 & VV6404Line Number
Frame Period (304 Lines)
FST
Frame Format (Border rows and columns enabled in example):FST
Start of Frame Line Format:Line Period (393 Pixel Periods - 30 fps, 471 Pixel Periods - 25 fps)37 (115) Pixels
4 Pixels33 (111) Pixels
Figure 16 : FST Pin Waveforms.
VV5404 & VV6404 Serial Control Bus
5.1 General DescriptionWriting configuration information to the video sensor and reading both sensor status and configuration information
back from the sensor is performed via the 2-wire serial interface.
Communication using the serial bus centres around a number of registers internal to the video sensor. These
registers store sensor status, set-up, exposure and system information. Most of the registers are read/write allowing
the receiving equipment to change their contents. Others (such as the chip id) are read only.
The main features of the serial interface include: Variable length read/write messages. Indexed addressing of information source or destination within the sensor. Automatic update of the index after a read of write message. Message abort with negative acknowledge from the master. Byte oriented messages.
The contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line -
see Section 4.3.4.
5.2 Serial Communication ProtocolThe video processor must perform the role of a communications master and the camera acts as either a slave receiver
or transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial clock video
processor frequency of up to 100 kHz. Since the serial clock is generated by the host it determines the data transfer
rate. The bus address for the sensor in VV6404 is 20H and for the serial E2 PROM containing the defect map it is A0H.
Data transfer protocol on the bus is shown below.
5.3 Data FormatInformation is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The internal data is produced
by sampling sda at a rising edge of scl. The external data must be stable during the high period of scl. The exceptions
to this are start (S) or stop (P) conditions when sda falls or rises respectively, while scl is high.
A message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start,
(Sr), followed by another message.
The first byte contains the device address byte which includes the data direction read, (r), ~write, (~w), bit. The device
address of VV6404 is fixed as 0010_000_[lsb]2 . The lsb of the address byte indicates the direction of the message.
If the lsb is set high then the master will read data from the slave and if the lsb is reset low then the master will write
data to the slave. After the r,~w bit is sampled, the data direction cannot be changed, until the next address byte with
a new r,~w bit is received.
The byte following the address byte contains the address of the first data byte (also referred to as the index). The
serial interface can address up to 128, byte registers. If the msb of the second byte is set the automatic increment
feature of the address index is selected.
