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VND7N04TR-E
OMNIFET :FULLY AUTOPROTECTED POWER MOSFET
September 2013 Rev 2 1/17
VND7N04, VND7N04-1
VNK7N04FM
"OMNIFET":
Fully autoprotected power MOSFET
Features
Linear current limitation Thermal shut down Short circuit protection Integrated clamp Low current drawn from input pin Diagnostic feedback through input pin ESD protection Direct access to the gate of the power
MOSFET (analog driving) Compatible with standard power MOSFET
Description
The VND7N04, VND7N04-1 and VNK7N04FM
are monolithic devices made using
STMicroeletronics VIPower M0 Technology,
intended for replacement of standard power
MOSFETS in DC to 50 KHz applications. Built-in
thermal shut-down, linear current limitation and
overvoltage clamp protect the chip in harsh
enviroments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
Type Vclamp RDS(on) Ilim
VND7N04
VND7N04-1
VNK7N04FMVVV
0.14Ω
0.14Ω
0.14ΩAAA
Table 1. Device summary
Part number Order code
VND7N04
VND7N04, VND7N04-1-E,
VND7N04-E, VND7N0413TR,
VND7N04TR-E
VND7N04-1 VND7N04-1
VNK7N04FM VNK7N04FM
Contents VND7N04, VND7N04-1, VNK7N04FM
2/17
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VND7N04, VND7N04-1, VNK7N04FM Block diagram 3/17 Block diagram
Figure 1. Block diagram
Electrical specification VND7N04, VND7N04-1, VNK7N04FM
4/17 Electrical specification
2.1 Absolute maximum rating
2.2 Thermal data
2.3 Electrical characteristics
Table 2. Absolute maximum rating
Symbol Parameter
Value
UnitDPAK
IPAK SOT-82FM
VDS Drain-source voltage (Vin = 0) Internally clamped V
Vin Input voltage 18 V Drain current Internally limited A Reverse DC output current -7 A
Vesd Electrostatic discharge (C = 100 pF,
R=1.5 KΩ) 2000 V
Ptot Total dissipation at Tc = 25°C 60 9 W Operating junction temperature Internally limited °C Case operating temperature Internally limited °C
Tstg Storage temperature -55 to 150 °C
Table 3. Thermal data
DPAK/IPAK SOT82-FM
Rthj-case Thermal resistance junction-case max 3.75 14 ° C/W
Rthj-amb Thermal resistance junction-ambient max 100 100 ° C/W
Table 4. Electrical characteristics: off
(-40 < Tj < 125° C unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCLAMP Drain-source clamp voltage ID = 200 mA Vin = 0 32 42 52 V
VCLTH Drain-source clamp threshold voltage ID = 2 mA Vin = 0 31 V
VINCL Input-source reverse clamp voltage Iin = -1 mA -1.1 -0.25 V
IDSS Zero input voltage drain current (Vin = 0) VDS = 13 V Vin = 0
VDS = 25 V Vin = 0
IISS Supply current from input pin VDS = 0 V Vin = 10V 250 550 μA
VND7N04, VND7N04-1, VNK7N04FM Electrical specification 5/17
Table 5. Electrical characteristics: on
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIN(th) Input threshold voltage VDS = Vin ID + Iin = 1 mA 0.8 3 V DS(on) Static drain-source on resistance
Vin = 10 V ID = 3.5A
Vin = 5 V ID = 3.5A
-40 < Tj < 25°C
Vin = 10 V ID = 3.5A
Vin = 5 V ID = 3.5A
Tj = 125°C
Table 6. Electrical characteristics: dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unitfs (1) Forward
transconductance VDS = 13V ID = 3.5A 2 5 S
Coss Output capacitance VDS = 13 V f = 1 MHz Vin = 0 250 500 pF Pulsed: Pulse duration = 300 μs, duty cycle 1.5%
Table 7. Electrical characteristics: switching
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on)
td(off) urn-on delay time
Rise time urn-off delay time
Fall time
VDD = 15 V Id = 3.5A
Vgen = 10 V Rgen = 10Ω
(see Figure 26)
td(on)
td(off) urn-on delay time
Rise time urn-off delay time
Fall time
VDD = 15 V Id = 3.5A
Vgen = 10 V Rgen = 1000Ω
(see Figure 26)
(di/dt)on T urn-on current slope VDD = 15 V ID = 3.5A
Vin = 10 V Rgen = 10Ω 50 A/μs T otal input charge VDD = 12 V ID = 3.5 A Vin = 10V 18 nC
Table 8. Electrical characteristics: source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSD (1) Forward on voltage ISD = 3.5 A Vin = 0 1.7 V
trr (2)
Qrr (2)
IRRM (2)
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3.5 A di/dt = 100 A/μs
VDD = 30 V Tj = 25°C
(see test circuit, Figure 28)
3.6 Pulsed: Pulse duration = 300 μs, duty cycle 1.5% Parameters guaranteed by design/characterization
Electrical specification VND7N04, VND7N04-1, VNK7N04FM
6/17
Table 9. Electrical characteristics: protection
Symbol Parameter Test conditions Min. Typ. Max. Unitlim Drain current limit Vin = 10 V VDS = 13V
Vin = 5 V VDS = 13V dlim (1) Step response
Current limit
Vin = 10V
Vin = 5V
Tjsh (1) Overtemperature
shutdown 150 °C
Tjrs (1) Overtemperature reset 135 °Cgf (1) Fault sink current Vin = 10 V VDS = 13V
Vin = 5 V VDS = 13Vas (1) Single pulse avalanche
energy
starting Tj = 25° C VDD = 20V
Vin = 10 V Rgen = 1 KΩ L = 30 mH 0.4 J Pulsed: Pulse duration = 300 μs, duty cycle 1.5%
VND7N04, VND7N04-1, VNK7N04FM Protection features 7/17 Protection features
During normal operation, the Input pin is electrically connected to the gate of the internal
power MOSFET. The device then behaves like a standard power MOSFET and can be used
as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small
DC current (Iiss) flows into the Input pin in order to supply the internal circuitry.
The device integrates: Overvoltage clamp protection: internally set at 42 V, along with the rugged avalanche
characteristics of the Power MOSFET stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly important when driving inductive
loads. Linear current limiter circuit: limits the drain current Id to Ilim whatever the Input pin
voltage. When the current limiter is active, the device operates in the linear region, so
power dissipation may exceed the capability of the heatsink. Both case and junction
temperatures increase, and if this phase lasts long enough, junction temperature may
reach the overtemperature threshold Tjsh. Overtemperature and short circuit protection: these are based on sensing the chip
temperature and are not dependent on the input voltage. The location of the sensing
element on the chip in the power stage area ensures fast, accurate detection of the
junction temperature. Overtemperature cutout occurs at minimum 150° C. The device
is automatically restarted when the chip temperature falls below 135°C. Status feedback: in the case of an overtemperature fault condition, a Status Feedback
is provided through the Input pin. The internal protection circuit disconnects the input
from the gate and connects it instead to ground via an equivalent resistance of 100 Ω.
The failure can be detected by monitoring the voltage at the Input pin, which will be
close to ground potential.
Additional features of this device are ESD protection according to the Human Body model
and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)).
Protection features VND7N04, VND7N04-1, VNK7N04FM
8/17
Figure 2. Thermal impedance for DPAK /
IPAK
Figure 3. Derating curve
Figure 4. Output characteristics Figure 5. Transconductance
Figure 6. Static drain-source on resistance
vs input voltage
Figure 7. Static drain-source on resistance
(part 1/2)
VND7N04, VND7N04-1, VNK7N04FM Protection features 9/17
Figure 8. Static drain-source on resistance
(part 2/2)
Figure 9. Input charge vs input voltage
Figure 10. Capacitance variations Figure 11. Normalized input threshold voltage
vs temperature
Figure 12. Normalized on resistance vs
temperature (part 1/2)
Figure 13. Normalized on resistance vs
temperature (part 2/2)
