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VND5N0713TR
OMNIFET FULLY AUTOPROTECTED POWER MOSFET
1/15June 2004
VND5N07/VND5N07-1
VNP5N07FI/K5N07FM
"OMNIFET":
FULLY AUTOPROTECTED POWER MOSFET
REV. 2
Table 1. General Features LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTION INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PIN DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN ESD PROTECTION DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTION
The VND5N07, VND5N07-1, VNP5N07FI and
VNK5N07FM are monolithic devices made using
STMicroelectronics VIPower M0 Technology,
intended for replacement of standard power
MOSFETS in DC to 50 KHz applications. Built-in
thermal shut-down, linear current limitation and
overvoltage clamp protect the chip in harsh
enviroments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
Figure 1. Package
Table 2. Order Codes
VND5N07/VND5N07-1/VNP5N07FI/K5N07FM
Figure 2. Block Diagram
Table 3. Absolute Maximum Ratings
Table 4. Thermal Data
3/15
VND5N07/VND5N07-1/VNP5N07FI/K5N07FM
ELECTRICAL CHARACTERISTICS (Tcase = 25°C unless otherwise specified)
Table 5. Off
Table 6. On (1)
Note:1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Table 7. Dynamic
Note:2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.
Table 8. Switching (3)
Note:3. Parameters guaranteed by design/characterization.
VND5N07/VND5N07-1/VNP5N07FI/K5N07FM
ELECTRICAL CHARACTERISTICS (cont’d)
Table 9. Source Drain Diode
Note:4. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% Parameters guaranteed by design/characterization.
Table 10. Protection
Note:6. Parameters guaranteed by design/characterization.
PROTECTION FEATURES
During normal operation, the Input pin is
electrically connected to the gate of the internal
power MOSFET. The device then behaves like a
standard power MOSFET and can be used as a
switch from DC to 50 KHz. The only difference
from the user’s standpoint is that a small DC
current (Iiss) flows into the Input pin in order to
supply the internal circuitry.
The device integrates: OVERVOLTAGE CLAMP PROTECTION:
internally set at 70V, along with the rugged
avalanche characteristics of the Power
MOSFET stage give this device unrivalled
ruggedness and energy handling capability.
This feature is mainly important when driving
inductive loads. LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current Id to Ilim whatever the Input pin
voltage. When the current limiter is active, the
device operates in the linear region, so power
dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold Tjsh. OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing the
chip temperature and are not dependent on the
input voltage. The location of the sensing
element on the chip in the power stage area
ensures fast, accurate detection of the junction
temperature. Overtemperature cutout occurs at
minimum 150°C. The device is automatically
restarted when the chip temperature falls below
135°C. STATUS FEEDBACK: In the case of an
overtemperature fault condition, a Status
Feedback is provided through the Input pin. The
internal protection circuit disconnects the input
from the gate and connects it instead to ground
via an equivalent resistance of 100 Ω. The
failure can be detected by monitoring the
voltage at the Input pin, which will be close to
ground potential.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)).
5/15
VND5N07/VND5N07-1/VNP5N07FI/K5N07FM
Figure 3. Thermal Impedance for DPAK/IPAK Figure 4. Thermal Impedance for ISOWATT220
Figure 5. Derating Curve Figure 6. Output Characteristics
Figure 7. Transconductance Figure 8. Static Drain-source On Resistance vs
Input Voltage
VND5N07/VND5N07-1/VNP5N07FI/K5N07FM
Figure 9. Static Drain-Source On Resistance Figure 10. Static Drain-Source On Resistance
Figure 11. Input Charge vs Input Voltage Figure 12. Capacitance Variations
Figure 13. Normalized Input Threshold Voltage
vs Temperature
Figure 14. Normalized On Resistance vs
Temperature
7/15
VND5N07/VND5N07-1/VNP5N07FI/K5N07FM
Figure 15. Normalized On Resistance vs
Temperature
Figure 16. Turn-on Current Slope
Figure 17. Turn-on Current Slope Figure 18. Turn-off Drain-Source Voltage Slope
Figure 19. Turn-off Drain-Source Voltage Slope Figure 20. Switching Time Resistive Load
VND5N07/VND5N07-1/VNP5N07FI/K5N07FM
Figure 21. Switching Time Resistive Load Figure 22. Switching Time Resistive Load
Figure 23. Current Limit vs Junction
Temperature
Figure 24. Step Response Current Limit
Figure 25. Source Drain Diode Forward
Characteristics
