VND5050KTR-E ,Double channel high side driver with analog current senseElectrical characteristics curves 163 Application information . . . . . 203.1 GND protecti ..
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WE9140A , TONE/PULSE SWITCHABLE DIALER WITH REDIAL
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VND5050JTR-E-VND5050K-E-VND5050KTR-E
Double channel high side driver with analog current sense
September 2013 Doc ID 12266 Rev 7 1/37
VND5050J-E
VND5050K-EDouble channel high side driver
for automotive applications
Features Main Inrush current active management by
power limitation Very low standby current 3.0 V CMOS compatible input Optimized electromagnetic emission Very low electromagnetic susceptibility In compliance with the 2002/95/EC
European directive Diagnostic functions Open drain status output On-state open load detection Off-state open load detection Thermal shutdown indication Protections Undervoltage shutdown Overvoltage clamp Output stuck to VCC detection Load current limitation Self limiting of fast thermal transients Protection against loss of ground and loss
of VCC Thermal shutdown Reverse battery protection (see Figure 28) Electrostatic discharge protection
Applications All types of resistive, inductive and capacitive
loads
DescriptionThe VND5050K-E and VND5050J-E are
monolithic devices made using
STMicroelectronics VIPower M0-5 technology.
they are intended for driving resistive or inductive
loads with one side connected to ground. Active CC pin voltage clamp protects the devices
against low energy spikes (see ISO7637 transient
compatibility table). The devices detect open load
condition both in on and off-state, when
STAT_DIS is left open or driven low. Output
shorted to VCC is detected in the off-state.
When STAT_DIS is driven high, STATUS pin is in
high impedance state.
Output current limitation protects the devices in
overload condition. In case of long overload
duration, the devices limit the dissipated power to
a safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the devices to recover normal operation as soon
as fault conditions disappear. Typical value with all loads connected.
Table 1. Device summary
Contents VND5050J-E / VND5050K-E2/37 Doc ID 12266 Rev 7
Contents Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VND5050J-E / VND5050K-E List of tables
Doc ID 12266 Rev 7 3/37
List of tables
Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Switching (VCC= 13V; Tj= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Status pin (VSD=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 14. Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 15. Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 16. PowerSSO-12™ thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. PowerSSO-24™ thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of figures VND5050J-E / VND5050K-E
4/37 Doc ID 12266 Rev 7
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Openload on-state detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. Openload off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 31. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24
Figure 33. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on). . . . 25
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 35. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 36. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 27
Figure 37. PowerSSO-24™ thermal impedance junction ambient single pulse (one channel on). . . . 28
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28
Figure 39. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 40. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 41. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 42. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 43. PowerSS0-24™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 44. PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VND5050J-E / VND5050K-E Block diagram and pin description
Doc ID 12266 Rev 7 5/37
Block diagram and pin description
Figure 1. Block diagram
Table 2. Pin function
Block diagram and pin description VND5050J-E / VND5050K-E
6/37 Doc ID 12266 Rev 7
Figure 2. Configuration diagram (top view)
Table 3. Suggested connections for unused and not connected pins Not recommended.
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 7/37
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = V OUTn - V CCn during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 4. Absolute maximum ratings
Electrical specifications VND5050J-E / VND5050K-E
8/37 Doc ID 12266 Rev 7
2.2 Thermal data
2.3 Electrical characteristics
8V .
Table 4. Absolute maximum ratings (continued)
Table 5. Thermal data
Table 6. Power section
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 9/37
PowerMOS leakage included. For each channel.
Table 7. Switching (VCC= 13V; Tj= 25°C)
Table 8. Status pin (VSD =0V)
Table 6. Power section (continued)
Electrical specifications VND5050J-E / VND5050K-E
10/37 Doc ID 12266 Rev 7
Table 9. Protections(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Table 10. Openload detection
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 11/37
Electrical specifications VND5050J-E / VND5050K-E
12/37 Doc ID 12266 Rev 7
Figure 5. Switching characteristics
Table 12. Truth table If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 13/37
Figure 6. Output voltage drop limitation
Table 13. Electrical transient requirements (part 1/3)
Table 14. Electrical transient requirements (part 2/3) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. Valid in case of external load dump clamp: 40V maximum referred to ground.
Electrical specifications VND5050J-E / VND5050K-E
14/37 Doc ID 12266 Rev 7
Table 15. Electrical transient requirements (part 3/3)
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 15/37
Figure 7. Waveforms
Electrical specifications VND5050J-E / VND5050K-E Doc ID 12266 Rev 7
2.4 Electrical characteristics curves
Figure 8. Off-state output current Figure 9. High level input current
Figure 10. Input clamp voltage Figure 11. Input high level
Figure 12. Input low level Figure 13. Input hysteresis voltage
VND5050J-E / VND5050K-E Electrical specifications
Figure 14. Status low output voltage Figure 15. On-state resistance vs T case
Figure 16. Status leakage current Figure 17. On-state resistance vs VCC
Figure 18. Status clamp voltage Figure 19. Openload on-state detection
threshold
Electrical specifications VND5050J-E / VND5050K-E Doc ID 12266 Rev 7
Figure 20. Openload off-state voltage
detection threshold
Figure 21.ILIM vs T case
Figure 22. Turn-on voltage slope Figure 23. Undervoltage shutdown
Figure 24. Turn-off voltage slope Figure 25. STAT_DIS clamp voltage
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 19/37
Figure 26. High level STAT_DIS voltage Figure 27. Low level STAT_DIS voltage
