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VNB10N07TR-E
OMNIFET :FULLY AUTOPROTECTED POWER MOSFET
VNB10N07/K10N07FM
VNP10N07FI/VNV10N07"OMNIFET":
FULLY AUTOPROTECTED POWER MOSFET
June 1998
BLOCK DIAGRAM (∗) LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTION INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PIN DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN ESD PROTECTION DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTIONThe VNB10N07, VNK10N07FM, VNP10N07FI
and VNV10N07 are monolithic devices made
using STMicroelectronics VIPower M0
Technology, intended for replacement of
standard power MOSFETS in DC to 50 KHz
applications. Built-in thermal shut-down, linear
current limitation and overvoltage clamp protect
the chip in harsh enviroments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
(∗) PowerSO-10 Pin Configuration : INPUT = 6,7,8,9,10; SOURCE = 1,2,4,5; DRAIN = TAB
1/14
ABSOLUTE MAXIMUM RATING
THERMAL DATA
ELECTRICAL CHARACTERISTICS (Tcase = 25 o C unless otherwise specified)
OFF
ON (∗)
VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N072/14
ELECTRICAL CHARACTERISTICS (continued)DYNAMIC
SWITCHING (**)
SOURCE DRAIN DIODE
PROTECTION
(∗) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %
(∗∗) Parameters guaranteed by design/characterization
VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N073/14
During normal operation, the Input pin is
electrically connected to the gate of the internal
power MOSFET. The device then behaves like a
standard power MOSFET and can be used as a
switch from DC to 50 KHz. The only difference
from the user’s standpoint is that a small DC
current (Iiss) flows into the Input pin in order to
supply the internal circuitry.
The device integrates: OVERVOLTAGE CLAMP PROTECTION:
internally set at 70V, along with the rugged
avalanche characteristics of the Power
MOSFET stage give this device unrivalled
ruggedness and energy handling capability.
This feature is mainly important when driving
inductive loads. LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current Id to Ilim whatever the Input
pin voltage. When the current limiter is active,
the device operates in the linear region, so
power dissipation may exceed the capability of
the heatsink. Both case and junction
temperatures increase, and if this phase lasts
long enough, junction temperature may reach
the overtemperature threshold Tjsh. OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing
the chip temperature and are not dependent on
the input voltage. The location of the sensing
element on the chip in the power stage area
ensures fast, accurate detection of the junction
temperature. Overtemperature cutout occurs at
minimum 150oC. The device is automatically
restarted when the chip temperature falls
below 135oC. STATUS FEEDBACK: In the case of an
overtemperature fault condition, a Status
Feedback is provided through the Input pin.
The internal protection circuit disconnects the
input from the gate and connects it instead to
ground via an equivalent resistance of 100 Ω.
The failure can be detected by monitoring the
voltage at the Input pin, which will be close to
ground potential.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit (with a small increase in RDS(on)).
PROTECTION FEATURES
VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N074/14
Thermal Impedance For ISOWATT220
Derating Curve
Transconductance
Thermal Impedance For D2PAK / PowerSO-10
Output Characteristics
Static Drain-Source On Resistance vs Input
Voltage
VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N075/14
Static Drain-Source On Resistance
Input Charge vs Input Voltage
Normalized Input Threshold Voltage vs
Temperature
Static Drain-Source On Resistance
Capacitance Variations
Normalized On Resistance vs Temperature
VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N076/14
Normalized On Resistance vs Temperature
Turn-on Current Slope
Turn-off Drain-Source Voltage Slope
Turn-on Current Slope
Turn-off Drain-Source Voltage Slope
Switching Time Resistive Load
VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N077/14
