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VN920B5TR-E
HIGH SIDE DRIVER
1/24October 2004
VN920-E
VN920B5-E / VN920SO-E
HIGH SIDE DRIVER
Rev. 1
Table 1. General Features CMOS COMPATIBLE INPUT PROPORTIONAL LOAD CURRENT SENSE SHORTED LOAD PROTECTION UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN OVERVOLTAGE CLAMP THERMAL SHUTDOWN CURRENT LIMITATION PROTECTION AGAINST LOSS OF GROUND
AND LOSS OF VCC VERY LOW STAND-BY POWER DISSIPATION REVERSE BATTERY PROTECTION (*) IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
DESCRIPTION
The VN920-E, VN920B5-E, VN920SO-E is a
monolithic device made by using
STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground. Active VCC pin voltage
clamp protects the device against low energy
spikes (see ISO7637 transient compatibility table).
Figure 1. Package
Active current limitation combined with thermal
shutdown and automatic restart protect the device
against overload. The device integrates an analog
current sense output which delivers a current
proportional to the load current. Device
automatically turns off in case of ground pin
disconnection.
Table 2. Order Codes
Note: (*) See application schematic at page 9.
VN920-E / VN920B5-E / VN920SO-E
2/24
Figure 2. Block Diagram
Table 3. Absolute Maximum Ratings
3/24
VN920-E / VN920B5-E / VN920SO-E
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
Figure 4. Current and Voltage Conventions
Table 4. Thermal Data1 ) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35μm thick).2 ) When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35μm thick).3 ) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35μm thick) connected to all VCC pins.4 ) When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35μm thick) connected to all VCC pins.
VN920-E / VN920B5-E / VN920SO-E
4/24
ELECTRICAL CHARACTERISTICS (8VTable 5. Power
Note:1. Vclamp and VOV are correlated. Typical difference is 5V.
Table 6. Switching (VCC =13V)
Table 7. Logic Input
5/24
VN920-E / VN920B5-E / VN920SO-E
ELECTRICAL CHARACTERISTICS (continued)
Table 8. VCC - Output Diode
Table 9. Protections (see note 1)
Note:1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles.
Table 10. Current Sense (9V≤VCC≤16V) (See Fig. 5)
Note:2. current sense signal delay after positive input slope.
VN920-E / VN920B5-E / VN920SO-E
6/24
Figure 5. IOUT/ISENSE versus IOUT
Figure 6. Switching Characteristics (Resistive load RL=1.3Ω)
7/24
VN920-E / VN920B5-E / VN920SO-E
Table 11. Truth Table
Table 12. Electrical Transient Requirements On VCC Pin
VN920-E / VN920B5-E / VN920SO-E
8/24
Figure 7. Waveforms
9/24
VN920-E / VN920B5-E / VN920SO-E
Figure 8. Application Schematic
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / (IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2 /RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT line is also required to prevent
that, during battery voltage transient, the current exceeds
the Absolute Maximum Rating.
Safest configuration for unused INPUT pin is to leave it
unconnected, while unused SENSE pin has to be
connected to Ground pin.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the VCC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
μC I/Os PROTECTION:
If a ground protection network is used and negative
transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the μC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of μC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of μC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHμC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
VN920-E / VN920B5-E / VN920SO-E
10/24
Figure 9. Off State Output Current Figure 10. High Level Input Current
Figure 11. Input Clamp Voltage
Figure 12. On State Resistance Vs Tcase
Figure 13. On State Resistance Vs VCC
Figure 14. Input High Level
11/24
VN920-E / VN920B5-E / VN920SO-E
Figure 15. Input Low Level
Figure 16. Turn-on Voltage Slope
Figure 17. Overvoltage Shutdown
Figure 18. Input Hysteresis Voltage
Figure 19. Turn-off Voltage Slope
Figure 20. ILIM Vs Tcase
VN920-E / VN920B5-E / VN920SO-E
12/24
Figure 21. P2 PAK Maximum turn off current versus load inductance
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
VIN, IL
Demagnetization Demagnetization Demagnetization

Partno	Mfg	Dc	Qty	Available	Descript
VN920B5TR-E \|VN920B5TRE	STM	N/a	10000	avai	HIGH SIDE DRIVER
VN920B5TR-E \|VN920B5TRE	ST,ST	N/a	10000	avai	HIGH SIDE DRIVER