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VIPER20ADIP-E-VIPER20ASP-E-VIPER20ASPTR-E
Fixed frequency off line converter
June 2006 Rev 2 1/34
VIPer20A-ESMPS primary I.C.
General features Adjustable switching frequency up to 200 kHz Current mode control Soft start and shutdown control Automatic burst mode operation in stand-by
condition able to meet “blue angel” norm (<1w
total power consumption) Internally trimmed zener reference Undervoltage lock-out with hysteresis Integrated start-up supply Over-temperature protection Low stand-by current Adjustable current limitation
DescriptionAll the devices are made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized, high voltage, Vertical Power MOSFET
(700V/ 0.5A).
Typical applications cover offline power supplies
with a secondary power capability of 10W in wide
range condition and 20W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the ability to operate in stand-by mode
without extra components.
Block diagram
Contents
VIPer20A-E2/34
Contents Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1 Drain pin (Integrated Power MOSFET drain): . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Source pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 VDD pin (power supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Compensation pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 OSC pin (oscillator frequency): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115.1 Current mode topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 High voltage start-up current suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 External clock synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 Primary peak current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.7 Over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VIPer20A-E Contents
3/34
Electrical over stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216.1 Electrical over stress ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227.1 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electrical data VIPer20A-E
4/34
1 Electrical data
1.1 Maximum rating
Table 1. Absolute maximum rating
VIPer20A-E Electrical data
5/34
1.2 Electrical characteristics
TJ = 25°C; VDD = 13V, unless otherwise specified
Table 2. Power section
(1) On Inductive Load, Clamped.
Table 3. Supply section
Table 4. Oscillator section
Electrical data VIPer20A-E
6/34
Table 5. Error amplifier section
Table 6. PWM comparator section
Table 7. Shutdown and overtemperature section
VIPer20A-E Thermal data
7/34
2 Thermal data
Table 8. Thermal data When mounted using the minimum recommended pad size on FR-4 board. On multylayer PCB.
Pin description VIPer20A-E
8/34
3 Pin description
3.1 Drain pin (Integrated Power MOSFET drain):
Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an
integrated high voltage current source which is switched off during normal operation. The
device is able to handle an unclamped current during its normal operation, assuring self
protection against voltage surges, PCB stray inductance, and allowing a snubberless operation
for low output power.
3.2 Source pin:
Power MOSFET source pin. Primary side circuit common ground connection.
3.3 VDD pin (power supply):
This pin provides two functions : It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below , the start-up current source is activated and the output power MOSFET is switched off
until the VDD voltage reaches 11V. During this phase, the internal current consumption is
reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to
ground. After that, the current source is shut down, and the device tries to start up by
switching again. This pin is also connected to the error amplifier, in order to allow primary as well as
secondary regulation configurations. In case of primary regulation, an internal 13V
trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a
voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to
stuck the output of the transconductance amplifier to the high state. The COMP pin
behaves as a constant current source, and can easily be connected to the output of an
optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the
error amplifier through the VDD voltage, which cannot overpass 13V . The output voltage
will be somewhat higher than the nominal one, but still under control.
3.4 Compensation pin
This pin provides two functions : It is the output of the error transconductance amplifier, and allows for the connection of a
compensation network to provide the desired transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the needed value with usual components value. As
stated above, secondary regulation configurations are also implemented through the
COMP pin. When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a
zero duty cycle for the power MOSFET. This feature can be used to switch off the
converter, and is automatically activated by the regulation loop (no matter what the
configuration is) to provide a burst mode operation in case of negligible output power or
open load condition.
VIPer20A-E Pin description
9/34
3.5 OSC pin (oscillator frequency):
An Rt-Ct network must be connected on that to define the switching frequency. Note that
despite the connection of Rt to VDD, no significant frequency change occurs for VDD varying
from 8V to 15V . It provides also a synchronisation capability, when connected to an external
frequency source.
Figure 1. Connection diagrams (top view)
Figure 2. Current and voltage convention
Typical circuit VIPer20A-E
10/34
4 Typical circuit
Figure 3. Offline power supply with auxiliary supply feedback
VIPer20A-E Operation description
11/34
5 Operation description
5.1 Current mode topology:
The current mode control method, like the one integrated in the devices, uses two control loops
- an inner current control loop and an outer loop for voltage control. When the Power MOSFET
output transistor is on, the inductor current (primary side of the transformer) is monitored with a
SenseFET technique and converted into a voltage VS proportional to this current. When VS
reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the
outer voltage control loop defines the level at which the inner loop regulates peak current
through the power switch and the primary winding of the transformer.
Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input
voltage feedforward characteristic of the current mode control. This results in improved line
regulation, instantaneous correction to line changes, and better stability for the voltage
regulation loop.
Current mode topology also ensures good limitation in case there is a short circuit. During the
first phase the output current increases slowly following the dynamic of the regulation loop.
Then it reaches the maximum limitation current internally set and finally stops because the
power supply on VDD is no longer correct. For specific applications the maximum peak current
internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in case there are current spikes caused by primary side
capacitance or secondary side rectifier reverse recovery time.
5.2 Stand-by mode
Stand-by operation in nearly open load conditions automatically leads to a burst mode
operation allowing voltage regulation on the secondary side. The transition from normal
operation to burst mode operation happens for a power PSTBY given by :
Where:
LP is the primary inductance of the transformer. FSW is the normal switching frequency.
ISTBY is the minimum controllable current, corresponding to the minimum on time that the
device is able to provide in normal operation. This current can be computed as :
tb + td is the sum of the blanking time and of the propagation time of the internal current sense
and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY
may be affected by the efficiency of the converter at low load, and must include the power
drawn on the primary auxiliary voltage. STBY 1---LPI2 STBYF SW= STBYbtd+ ()VINp
--------- --------------------=
Operation description VIPer20A-E
12/34
As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase
above the 13V regulation level, forcing the output voltage of the transconductance amplifier to
low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power
switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as
VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates
again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty
cycle is much lower than the minimum one when in normal operation. The equivalent switching
frequency is also lower than the normal one, leading to a reduced consumption on the input
main supply lines. This mode of operation allows the VIPer20A-E to meet the new German
"Blue Angel" Norm with less than 1W total power consumption for the system when working in
stand-by mode. The output voltage remains regulated around the normal level, with a low
frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because
of the output capacitors and low output current drawn in such conditions.The normal operation
resumes automatically when the power gets back to higher levels than PSTBY.
5.3 High voltage start-up current suorce
An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits which are
placed into a standby mode with reduced consumption and also provided to the external
capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage
threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The
start-up current generator is switched off, and the converter should normally provide the
needed current on the VDD pin through the auxiliary winding of the transformer, as shown on
(see Figure 11).
In case there are abnormal conditions where the auxiliary winding is unable to provide the low
voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the
external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the
device goes back to the inactive state where the internal circuits are in standby mode and the
start-up current source is activated. The converter enters a endless start-up cycle, with a start-
up duty cycle defined by the ratio of charging current towards discharging when the VIPer20-E
tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle
while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage.
This low value start-up duty cycle prevents the application of stress to the output rectifiers as
well as the transformer when a short circuit occurs.
The external capacitor CVDD on the VDD pin must be sized according to the time needed by the
converter to start up, when the device starts switching. This time tSS depends on many
parameters, among which transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin. The following formula can be used for
defining the minimum capacitor needed:
where:
IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the converter when the device begins to switch. Worst case is
generally at full load.
VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value). VDDDDtSS DDhyst
-------------------->
VIPer20A-E Operation description
13/34
The soft start feature can be implemented on the COMP pin through a simple capacitor which
will be also used as the compensation network. In this case, the regulation loop bandwidth is
rather low, because of the large value of this capacitor. In case a large regulation loop
bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high
performance compensation network together with a separate high value soft start capacitor.
Both soft start time and regulation loop bandwidth can be adjusted separately.
If the device is intentionally shut down by tying the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff.
This voltage can be used for supplying external functions, provided that their consumption does
not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state
until the input voltage is removed.
5.4 Transconductance error amplifier
The VIPer20A-E includes a transconductance error amplifier. Transconductance Gm is the
change in output current (ICOMP) versus change in input voltage (VDD). Thus:
The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:
This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer20A-E is 1.5 mA/V typically.
Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances.
An impedance Z can be connected between the COMP pin and ground in order to define the
transfer function F of the error amplifier more accurately, according to the following equation
(very similar to the one above):
F(S) = Gm x Z(S)
The error amplifier frequency response is reported in for different values of a simple resistance
connected on the COMP pin. The unloaded transconductance error amplifier shows an internal
ZCOMP of about 330KΩ . More complex impedance can be connected on the COMP pin to
achieve different compensation level. A capacitor will provide an integrator function, thus
eliminating the DC static error, and a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20
As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to
avoid any high frequency interference.
Is also possible to implement a slope compensation when working in continuous mode with
duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the
classical compensation network, and Q1 is injecting the slope compensation with the correct
polarity from the oscillator sawtooth.m COMPDD
-------------------= COMPV COMPI COMP
-------------------- 1-------- ∂V COMP
∂VDD- -----------------------×==
Operation description VIPer20A-E
14/34
5.5 External clock synchronization:
The OSC pin provides a synchronisation capability when connected to an external frequency
source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.
If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is
sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through
the optotransistor.
5.6 Primary peak current limitation
The primary IDPEAK current and, consequently, the output power can be limited using the
simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on
the COMP pin in order to limit the primary peak current of the device to a value:
where:
The suggested value for R1+R2 is in the range of 220KΩ.
5.7 Over-temperature protection
Over-temperature protection is based on chip temperature sensing. The minimum junction
temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is
170ºC. The device is automatically restarted when the junction temperature decreases to the
restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13) DPEAK COMP 0.5–ID
--------------------------------= COMP 0.6 R1 R2+2
-------------------×=
VIPer20A-E Operation description
15/34
5.8 Operation pictures
Figure 5. VDD Regulation point Figure 6. Undervoltage lockout
Figure 9. Breakdown voltage vs temperature Figure 10. Typical frequency variation
Operation description VIPer20A-E
16/34
Figure 11. Behaviour of the high voltage current source at start-up
Figure 12. Start-up waveforms
VIPer20A-E Operation description
17/34
Figure 13. Over-temperature protection
