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V320
8-Bit Registered Bus Transceiver
V320 8-Bit Registered Bus Transceiver April 1998 Revised October 1998 V320 8-Bit Registered Bus Transceiver General Description Features The V320 is an 8-bit universal bus transceiver designed for � Independent registers for A and B buses high speed interfacing with the VME320 backplane. It has � Multiplexed real-time and stored data output characteristics optimized for driving large capacitive � Guaranteed output skew loads and features modified input levels (V /V ) for IH IL � Guaranteed MOS (Multiple Output Switching) Specifica- increased noise immunity and reduced input skew. The tions V320 functionality consists of bus transceiver circuits with � Output switching specified for both 50 pF and 250 pF, 3-STATE, D-type flip-flops, and control circuitry arranged and 500 pF loads for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus � Guaranteed simultaneous switching noise level (V / OLP will be clocked into the registers as the appropriate clock V ) and dynamic threshold performance (V /V ) OLV IHD ILD pin goes to a high logic level. OE and direction pins are � Glitch free power up/down high impedance for live inser- provided to control the transceiver function. In the trans- tion ceiver mode, data present at the high impedance port may � BiCMOS technology for high drive and low power dissi- be stored in either the A or B register or in both. The select pation controls can multiplex stored and real time (transparent mode) data. The direction control determines which bus � −40°C to 85°C commercial temperature and V specifi- CC will receive data when the enable control OE is active cations LOW. In the isolation mode (OE HIGH) A data may be � Modified specifications across V and temperature CC stored in the B register and/or B data may be stored in the (V = 5.0V ±1%, T = 25°C ± 20°C) present more realis- CC A register. tic system conditions � Available in TSSOP (MTC) Ordering Code: Order Number Package Number Package Description V320MTC MTC24 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description D Direction A-to-B (High) B-to A (Low) OE Output Enable (Active LOW) CLKAB/SELAB A-to-B Clock/Select CLKBA/SELBA B-to-A Clock/Select A0–7 A Inputs/Outputs (TTL) B0–7 B Inputs/Outputs (TTL) © 1998 DS500149.prf
