UC3845AD1013TR ,HIGH PERFORMANCE CURRENT MODE PWM CONTROLLERBlock Diagram (toggle flip flop used only in UC3844A and UC3845A)7ViUVLO34V85VVREF5 S/RREFGROUND 5V ..
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UC3845AD8TRG4 ,Current Mode PWM Controller 8-SOIC 0 to 70Maximum ratings table with maximum negative voltage and GND pin notes..... 6Changes from Revision B ..
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UC3845AJ ,Current Mode PWM Controller SLUS223E–APRIL 1997–REVISED JANUARY 20175 Device Comparison TableUVLOTURNON AT 16 V TURNON AT 8.4 ..
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UN2213 ,Composite DeviceAbsolute Maximum Ratings T = 25°CaParameter Symbol Rating UnitCollector-base voltage (Emitter open ..
UN2213 ,Composite DeviceTransistors with built-in ResistorUNR221x Series (UN221x Series)Silicon NPN epitaxial planar transi ..
UN2214 ,Composite DeviceAbsolute Maximum Ratings T = 25°CaParameter Symbol Rating UnitCollector-base voltage (Emitter open ..
UN2215 ,Composite DeviceTransistors with built-in ResistorUNR221x Series (UN221x Series)Silicon NPN epitaxial planar transi ..
UN2216 ,Composite DeviceElectrical Characteristics T = 25°C ± 3°CaParameter Symbol Conditions Min Typ Max UnitCollector-ba ..
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UC2842A-UC2842AD1-UC2843A-UC2843AD1-UC2843AD1013TR-UC2844A-UC2844AD1-UC2844AD1013TR-UC2845A-UC3842A-UC3842AD1013TR-UC3843A-UC3843AD1-UC3843AD1013TR-UC3844A-UC3844AD1-UC3844AD1013TR-UC3845AD1-UC3845AD1013TR
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
1/16
UC284XA
UC384XAMay 2004
FEATURES TRIMMED OSCILLATOR DISCHARGE
CURRENT CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD
COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT
UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS LOW START-UP CURRENT (< 0.5mA)
DOUBLE PULSE SUPPRESSION
DESCRIPTIONThe UC384xA family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally im-
plemented circuits include a trimmed oscillator for
precise DUTY CYCLE CONTROL under voltage
lockout featuring start-up current less than 0.5mA,
a precision reference trimmed for accuracy at the
error amp input, logic to insure latched operation,
a PWM comparator which also provides current
limit control, and a totem pole output stage de-
signed to source or sink high peak current. The
output stage, suitable for driving N-Channel MOS-
FETs, is low in the off-state.
Differences between members of this family are
the under-voltage lockout thresholds and maxi-
mum duty cycle ranges. The UC3842A and
UC3844A have UVLO thresholds of 16V (on) and
10V (off), ideally suited off-line applications The
corresponding thresholds for the UC3843A and
UC3845A are 8.5 V and 7.9V. The UC3842A and
UC3843A can operate to duty cycles approaching
100%. A range of the zero to < 50 % is obtained by
the UC3844A and UC3845A by the addition of an
internal toggle flip flop which blanks the output off
every other clock cycle.
NOT FOR NEW DESIGNHIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)REV. 5
UC384XA - UC284XA
Table 2. Absolute Maximum Ratings* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
Figure 3. DIP-8/SO-8 Pin Connection (Top view)
Table 3. Pin Description
3/16
UC384XA - UC284XA
Table 4. Thermal Data
Table 5. Electrical Characteristcs ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
UC384XA - UC284XANotes:1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close
to Tamb as possible. These parameters, although guaranteed, are not 100% tested in production. Parameter measured at trip point of latch with VPIN2 = 0. Gain defined as : A = ΔVPIN1/ΔVPIN3; 0 ≤ VPIN3 ≤ 0.8V Adjust Vi above the start threshold before setting at 15 V.
Table 5. Electrical Characteristcs (continued)( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA;
0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
5/16
UC384XA - UC284XA
Figure 4. Open Loop Test Circuit.High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ
potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 5. Oscillator Frequency vs Timing
Resistance
Figure 6. Maximum Duty Cycle vs Timing
Resistor
Figure 7. Oscillator Discharge Current vs.
Temperature.
Figure 8. Error Amp Open-Loop Gain and
Phase vs. Frequency.
UC384XA - UC284XA
Figure 9. Current Sense Input Threshold vs.
Error Amp Output Voltage.
Figure 10. Reference Voltage Change vs.
Source Current..
Figure 11. Reference Short Circuit Current vs.
Temperature..
Figure 12. Output Saturation Voltage vs. Load
Current.
Figure 13. Supply Current vs. Supply Voltage.
7/16
UC384XA - UC284XA
Figure 14. Output Waveform. Figure 15. Output Cross Conduction
Figure 16. Oscillator and Output Waveforms.
Figure 17. Error Amp Configuration.
UC384XA - UC284XA
Figure 18. Under Voltage Lockout.
Figure 19. Current Sense Circuit.Peak current (is) is determined by the formula
A small RC filter may be required to suppress switch transients.
Figure 20. Slope Compensation Techniques. Smax 1.0VS
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