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UAA3220TS
Frequency Shift Keying FSK/Amplitude Shift Keying ASK receiver
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
FEATURES Low cost single-chip ASK or FSK receiver Superheterodyne architecture with high integration level Few external low cost components and crystal required Wide supply voltage range Low power consumption Wide frequency range, 250to 920 MHz High sensitivity IF bandwidth determined by application High selectivity Automotive temperature range SSOP24 package.
Applications Keyless entry systems Car alarm systems Remote control systems Security systems Telemetry systems Wireless data transmission Domestic appliance.
GENERAL DESCRIPTIONThe UAA3220TS is a fully integrated single-chip receiver,
primarily intended for use in VHF and UHF systems. supports both Amplitude Shift Keying (ASK) and
Frequency Shift Keying (FSK) demodulation. connecting DEMO1 (pin 10) to ground during
realisation of the receiver module the UAA3220TS works
as an ASK receiver (see Fig.10). By connecting pin 10 as
shown in Fig.9 the UAA3220TS works as an FSK receiver.
The UAA3220TS incorporates a crystal stabilized local
oscillator, frequency multiplier, balanced mixer, post mixer
amplifier, limiter, Received Signal Strength Indicator
(RSSI), FSK demodulator, data filter, data slicer and
power down circuit.
QUICK REFERENCE DATA
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
ORDERING INFORMATION
BLOCK DIAGRAM
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
PINNING
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
FUNCTIONAL DESCRIPTION
MixerThe mixer is a single-balanced emitter-coupled mixer with
internal biasing. Matching of the RF source impedance to
the mixer input requires an external matching network.
OscillatorThe oscillator is based on a transistor connected in
common collector configuration followed by a cascode
stage driving a tuned circuit. The voltage at this tuned
circuit drives the frequency multiplier. The bias current of
the oscillator is set by an off-chip resistor (R40 in the
application diagram of Fig.9) to a typical value of 260 μA at
433.92 MHz (R40= 1.8 kΩ). The oscillator frequency is
controlled by an off-chip overtone crystal (X40). Off-chip
capacitors between base and emitter (C42) and ground
(C41) make the oscillator transistor appear as having
negative resistance at small signal levels. This causes the
oscillator to start. A parallel resonance circuit (L40 and
C41) connected to the emitter of the oscillator transistor
prevents oscillation at the fundamental frequency of the
crystal. The LC tank circuit at the output of the oscillator is
used to select either the fundamental, the second or the
third harmonic of the oscillator frequency.
Frequency multiplierThe frequency multiplier is an emitter-coupled transistor
pair driving an off-chip balanced tuned circuit. The bias
current of this emitter coupled pair is set by an off-chip
resistor (R50) to a typical value of 350 μA at 433.92 MHz
(R50= 1.2 kΩ). The oscillator output signal is AC-coupled
to one of the inputs of the emitter-coupled pair. The other
input is connected to ground via an on-chip capacitor.
The output voltage of the frequency multiplier drives the
switching stage of the mixer. The bias voltage at this point
is set by an off-chip resistor (R51) to allow sufficient
voltage swing at the mixer outputs.
Post mixer amplifierThe Post Mixer Amplifier (PMA) is a differential input,
single-ended output amplifier. Amplifier gain is provided in
order to reduce the influence of the limiter noise figure on
the total noise figure.
LimiterThe limiter is a single-ended input multiple stage amplifier
with high total gain. Amplifier stability is achieved by
means of an external DC feedback capacitor (C21), which
is also used to determine the lower limiter cut-off
frequency. An RSSI signal proportional to the limiter input
signal is provided. Figure 3 shows the DC voltage at pin18
(RSSI) as a function of the input voltage (RMS value) at
pin 20 (LIN). It also gives the typical IF of 10.7 MHz.
The lower knee of the level curve (see Fig.3) is determined
by the effective noise bandwidth and is, consequently,
slightly higher.
IF filterIF filtering with high selectivity is realized by means of an
external ceramic filter (X20), which feeds the IF from the
PMA to the limiter.
FM demodulatorComing from the limiter the FSK signal is fed differential to
the input of the FM demodulator. After buffering the signal
is fed to a phase detector. The phase shift is generated by
an external LC combination connected to DEMO1 (pin 10)
and DEMO2 (pin 11). The baseband signal is coupled out
single ended via an output buffer and is fed to the FSK
input of the ASK/FSK switch.
ASK/FSK switchThe selection of either ASK or FSK reception will be done
by the DEMO1 (pin 10). Grounding this pin to 0 V will
switch the IC to ASK mode. Additional the FM demodulator
and parts of the data slicer will be switched off. In FSK
mode DEMO1 (pin 10) is connected to DEMO2 (pin 11)
via a LC combination (see Fig.9).
Data filtersAfter demodulation a two-stage data filtering circuit is
provided in order to suppress unwanted frequency
components. Two RC low-pass filters with on-chip
resistors are provided which are separated by a buffer
stage.
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
Data slicerData detection is provided by means of a level comparator
with adaptive slice reference. After the first data filter stage
the pre-filtered data is split into two paths. One passes the
second data filter stage and is fed to the positive
comparator input. The other path is fed to an integration
circuit with a large time constant in order to derive the
average value (DC component) as an adaptive slice
reference which is presented to the negative comparator
input. The internal buffer provides 13 dB AC voltage gain.
The adaptive reference allows to detect the received data
over a large range of noise floor levels. The integration
circuit consists of a simple RC low-pass filter with on-chip
resistors. The data slicer output is designed with internal
pull-up.
RSSI bufferThe RSSI buffer is an amplifier with a voltage gain of 0 dB.
At FSK receive mode the RSSI output provides a field
strength indication. It has an output impedance of 10 kΩ.
Figure 3 shows the level curve (RSSI curve) as a function
of the limiter input voltage (RMS value).
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134).
Note Machine model: C= 200 pF, R=0 Ω and L= 0.75 μH; pins are connected to GND and VCC.
THERMAL CHARACTERISTICS
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
DC CHARACTERISTICSVCC= 2.7 V; Tamb =25 °C; for application diagram see Figs9 and 10; crystal disconnected; unless otherwise specified.
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
Notes For fi(RF)= 868.35 MHz all values+ 0.6 mA. Crystal connected; oscillator and multiplier active. Pin DEMO1 connected to pin DEMO2 via tank circuit. Pin DEMO1 short circuited to ground. The given values are applicable for FSK reception mode. In ASK mode pin 10 is short circuited to ground. No modulation and fIF= 10.7 MHz.
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
AC CHARACTERISTICSVCC= 2.7 V; Tamb =25 °C; for application diagram see Figs9 and 10; fi(RF)= 433.92 MHz (see Table 4) and
fi(RF)= 868.35 MHz (see Table 5); fmod=1 kHz square wave; unless otherwise specified.
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
Notes 100% AM modulation (ASK); available power from generator into a 50 Ω load. With external matching network, to transform the impedance to 50Ω. Δf=10 kHz; available power from generator into a 50 Ω load. Measured at the RF input connector of the test board into a 50 Ω load; fi(RF)=25 MHzto1 GHz. The data frequency range can be varied by changing C30to C32 (see Figs9 and 10) to match other bit rates.
Data frequency determined by data slicer application. ton=50 ms; toff= 138 ms; P= Psens+3 dB. The given turn-on time is only valid during strobing by pin PWD; if the IC is strobed on and off by the supply voltage
the turn-on time will be longer. LC tank circuit (L60, C60) tuned to maximum phase slope. GPMA is typically 6 dB lower when measured in the application, because of the load of the ceramic filter.
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
INTERNAL CIRCUITRY
Table 1 Equivalent pin circuits and pin voltages for rough test of printed-circuit board; VCC= 2.7 V; no input signal
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
TEST INFORMATION
Tuning proceduresTUNING PROCEDURE FOR AC TESTS Turn on the signal generator (fi(RF)= 433.92or 868.35 MHz; no modulation; RF input level= −50 dBm). Tune first C50 (multiplier tank circuit), second C11 (RF stage input) to obtain a peak IF voltage at pin FA.
TUNING PROCEDURE FOR ASK RECEPTION Make sure that pin DEMO1 is short circuited to ground. Turn on ASK modulation and check that data is appearing on the DATA output pin and proceed with the AC tests.
TUNING PROCEDURE FOR FSK RECEPTION Make sure that pins DEMO1 and DEMO2 are connected by the LC tank circuit. Turn on FSK modulation (Δf=10 kHz; RF input level= −103 dBm). Tune C61 (or L60) (phase shifter LC tank circuit) to obtain a peak LF voltage at pin CPC. Check that data is appearing on pin DATA and proceed with the AC tests.
AC test conditions
Table 2 Test signals
The reference signal level Pref for the following tests is defined as the minimum input level in dBm to give a
BER≤3×10−2 (e.g. 60 bit errors per second for 2000 bits/s). All test signal levels refer to 50 Ω load condition.
Philips Semiconductors Product specification
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver UAA3220TS
Table 3 Tests and results
P1 is the maximum available power from signal generator 1 at the input of the test board; P2 is the maximum available
power from signal generator 2 at the input of the test board.
Notes The voltage at pin PWD of the test circuit alternates between operating mode: on (50 ms; 0 V) and off (138 ms; VCC);
see Fig.4. Probe of spectrum analyzer connected to pin FA (pin 22). Spectrum analyzer connected to the input of the test board.
