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UA9708PCFSCN/a2avai4.75 V to 15 V, 6-channel 8-bit uP compatible A/D converter


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UA9708PC
4.75 V to 15 V, 6-channel 8-bit uP compatible A/D converter
National _
I Semiconductor
pA9708
6-Channel 8-Bit p,P Compatible A/ D Converter
General Description Features
The “A9708 is a single slope 8-bit, 6-channel ADC subsys- n MPU compatible
tem that provides all of the necessary analog functions for a u Excellent linearity over full temperature
microprocessor-based data control system. The device range i0.2% maximum
uses an external microprocessor system to provide the nec- a Typical 300 M5 conversion time per channel
essary addressing, timing and counting functions and in- a Wide dynamic range includes ground
cludes a 1-of-8 decoder, 6-channel analog multiplexer, sam- n Auto-zero and full-scale correction capability
ple and hold, ramp in.teg.rator, pr.tt?.slo'.1 Temp reference, and Ratiometric conversion-no precision reference
a comparator on a single monolithic chip. require d
Single-supply operation
TTL compatible
Does not require access to data bus or address bus
Connection Diagram
All Packages '
N I Order Number M9708DC or pA97OBDM
“-1 1 16 -A0 See NS Package Number J1GA
AZ- 2 " -ll
- Order Number pA9708PC
“W srhRT 3 " 'Vcc See NS Package Number N16E
k- 4 I3 "-tt
GND- 5 12 -t3
RREF_ 6 It -14
RAMP STOP- 7 IO .-t5
TtJH/1iH09-2
(T up View)
Block Diagram
RAMP START
(FROM MPU)
.lq.---M.-.-----m.-----qt.-- ---"'---".------T
RAMP STOP
(T0 MPU)
SAN PLE I
23233:; l REF COMPARATOR
ANALOG
INPUTS
CONSTANT
CURRENT "..--. Va:
SOURCE j
DIGHAL 1-OF-8 REFERENCE
ADDRESS ADDRESS DECODER CURRENT i-
(FROM UN) GENERATOR
b----.-.-- --..-i.rt.--q..--. - o.-..---..------'
RREF iii” (RAMP CAPACITOR)
Voc VREF *Vcc = =
TL/H/10409-1
eozevfi
pA9708
Absolute Maximum Ratings (Note1)
ll MllltarylAerospace specified devices are required,
please contact the National Semlttondutttor Sales
OftlttefDlMrlbutttrs for availability and specifications.
Supply Voltage (Vcc) 18V
Comparator Output (Ramp Stop) - 0.3V to + 18V
Analog Input Range - 0.3V to + 30V
Digital Input Range - 0.3V to + 30V
Output Sink Current 10 mA
Storage Temperature Range -65''C to + 150°C
Continuous Total Dissipation
Ceramic DIP Package
Molded DIP Package
900 mW
1000 mW
Electrical Characteristics
Pin Temperature
Ceramic DIP (Soldering, 60 Sec.)
Molded DIP (Soldering, 10 Sec.)
Operating Ratings (Note1)
Operating Temperature Range
M9708PC, pA9708DC ty'C to + 70"C
pA9708DM - 55°C to + 125°C
Supply Voltage (Vcc) 4.75V to 15V
Reference Voltage
(VREF) (Note 2) 2.8V to 5.25V
Ramp Capacitor (CH) 300 pF
Reference Current (In) 12 pA to 50 p.A
Analog Input Range 0V to VREF
Ramp Stop Output Current 1.6 mA
Over recommended operating conditions, VCC = 5.0V, --55''G S TA s; + 125°C for HA9708DM and trc tC TA s +70°C for
pA97OBDC or pA9708PC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
EA Conversion Accuracy 8:; Elm; Jam'"'""' , th2 , 0.3 %
En Linearity 3:11:21qu t" l 0.08 i 0.2 %
VOSM Multiplexer Input Offset Voltage Channel ON 2.0 4.0 mV
tt Ctmvarsion Time per Channel 3335935535, id)', 1: V5531,“ 296 350 p s
tA Acquisition Time C... = 1000 pF 20 40 ps
IA Acquisition Current 150 p.A
to Ramp Start Delay Time 100 ns
tM Multiplexer Address Time 1 .0 ps
VIH Digital Input HIGH Voltage A0, A1, A2, Ramp Start 2.0 V
" Digital Input LOW Voltage AO, Al, A2, Ramp Start 0.8 V
IB Analog Input Current Channel ON or OFF - 3.0 - 1.0 pA
IIL Input LOW Current AO, A1, A2, Ramp Start = 0.4V _ 15 -5 p.A
le, Input HIGH Current AO, A1, A2, Ramp Start = 5.5V 1.0 pA
los Input Offset Current 1.0 3.0 FLA
IOH Comparator Logic "I " VOH = 15V 10 M A
Output Leakage Current
VOL Comparator Logic "0" OutputVoltage IOL = 1.6 mA 0.4 V
PSRR Power Supply Rejection Ratio (Note 5) 40 dB
iazsixs'sng" (Note6) so as
Ice Power Supply Current Vcc = 5V to 15V, 10 = 0 7.5 15 mA
cm Input Capacitance 3.0 pF
COUT Comparator Output Capacitance 5.0 pF
Note 1: Absoute Maximum Ratings indicate limits beyond which damage to the device may occuv. Operating Ratings indicate conditions tor which the device is
intended to be functional, but do not guarantee specific performance limits.
Not. 2.. VREF should not exceed Vcc - 2V.
Note 3: Conversion accuracy is dBfinBd as the deviations from a straight line drawn between the points defined by channel address 000 (0 scale) and channel
address 111 (full scale) for all channels.
Note 4: Linearity is defined as the deviation from a straight line drawn between the o and full scale points for each channel.
Note 5: Power supply reiecticn ratio is dMined as the conversion error contributed by power supply voltage variations while resolving mid scale on any channel.
Note 6: Cross Talk between channels = 20 log WC”
Timing Diagram and Test Circuits
-2v ff
mar sum
T"""""sss
ht: - 0.7V
CAPACITOR
Vac H-
RANP STOP
th4Y--,
l----e----/
TL/HM0409-7
FIGURE 1. Equivalent Tlmlng Waveform for
Test Circuits and Applicatlons
ANALOG mm:
mwumuzm
A0l1Vccl2|3|415|5
M9708 ery
RAMP mp
A1 " START cu mo Rm STOP hitr um
Itll um
- - osv
comet yo man uru
(THING COMPATIBLE WITH FIGURE "
Input Timing:
tA > 400 11.5
TLIH/10409-8
2kfl + 3.3m
= 5 - 3.1
t00kft
VREF = ( ) 5V = 3.1
In =19pA
tRImax = full scale ramptime
= 0.01 x 10-5
19 M Io-e
Note: For evaluation purposesthe ramp start timing generation can be im-
plemented with an LMSSS timer (astabte operation) or MPU evaluation kit,
and a time interval meter tor ramp time measurement The TIM meter will
measure the time between to 0 to 1 transition of the ramp start and the 1 to
o transition 01 the ramp stop. The ramp stop is open collector. and must
have an external pull-up resistor to Vcc-
FIGURE 2. Stow Speed Evaluation Clrcult
tor Ratlometrlc Operation
. 1"?"111 11
X 3.1=1.6ms
A0 " Ya: I2
RAMP RAMP
A1 A2 sum ci, cm Rerrlmh'%r
300 ie
TL/H/10409-9
FIGURE 3. Llnearity/Acquisition Tlmel
Conversion Time Test Circuit
osv blas
Mllhx I2 I3 It I5 l6
“A9708
RAMP RAuP
A1 A2 smt cH cm tttttr stop her
tto ---.
M 2.75v
f'l low
osv - +5v +1sv -
Yo VIH- Mb Ir,
TL/H/10409-10
FIGURE 4. Static Measurements
Functional Description
This Analog to Digital Converter is a singIe-slope 8-bit, 6-
channel A/D converter that provides all of the necessary
analog functions for a microprocessor-based data/control
system. The device uses the processor system to provide
the necessary addressing, timing and counting functions
and includes a 1.01-8 decoder, 8-channel analog multiplex-
er. sample and hold, precision current reference. ramp inte-
grator and comparator on a single monolithic chip.
Applications that require auto-zero or auto-calibration, (See
Figures 5-8) can use selection of address 000 and 111, for
input address lines M-M, in conjunction with the arithme-
tic capability of a microprocessor to provide ground and
scaling factors. Address 0, o, O internally connects the input
of the ramp generator to ground and may be used for zero
offset correction in subsequent conversions. Address I, l,
1, internally connects the input of the ramp generator to the
voltage reference, VREF, and may be used for scale factor
correction in subsequent conversions. For the following, re-
fer to the Functional Block Diagram.
Six separate external analog voltage inputs may come into
terminals ll-lt, and the specific analog input to be conven-
ed is selected via address terminals AO-AZ. The analog
input voltage level is transferred to the external ramp capac-
itor connected to pin 4 when the input to the ramp start
terminal (pin 3) is at a logic 0 (See Figure t). The time to
charge the capacitor is the acquisition time which is a func-
tion of the output impedance of an amplifier internal to the
A/ D converter and the value of the capacitor. After charging
the external capacitor the ramp start terminal is switched to
a logic 1 which introduces a high impedance between the
analog input voltage and the external capacitor.
The capacitor begins to discharge at a controlled rate. The
controlled rate of discharge (ramp) is established by the ex-
ternal reference voltage, the external reference resistor. the
value of the external capacitor and the internal leakage of
the Af D converter, Connected to the capacitor terminal is a
sozsvfi
p.A9708
Functional Description (Continued)
Auto-Zero and Full-Scale Features
COUNT n
VR_:r Yer INPUTV
TL/hi/INN-il
No Zero Offset
No Full-Scale Error
Count (n) = V_m: x 256
FIGURE 5. Ideal Transfer Functlon
comparator internal to the A/D converter with its output go-
ing to the ramp stop terminal (pin 7). The comparator output
is a logic one when the capacitor is charged and switches to
a logic 0 when the capacitor is in a discharged state. The
ramp time is from the time when ramp start goes HIGH (log-
ic "I") to when ramp stop goes LOW (logic "0"). The micro-
processor must be programmed to determine this conver-
sion time. The ideal (no undesirable internal source imped-
ances, leakage paths, errors on levels where comparator
switches or delay time) conversion time is calculated as fol-
Ramp Time = V1 'j,-:
Where V1 = Analog Input Voltage Being Measured
CH = External Ramp Capacitor
I = Vcc - VREF
Where Vcc = Power Supply Voltage
VREF = Reference Voltage
RREF = Reference Resistor
In actual use the errors due to a nonideai Al D converter can
be minimized by using a microprocessor to make the calcu-
lations. (See Figures 5 through 8.)
Channel Selection
Input Address Llno Selected
A2 A1 A0 Analog Input
0 o 0 Ground
0 0 1 I1
0 1 0 l2
0 1 1 l3
1 0 0 I4
1 0 1 IS
1 1 I) I6
1 1 1 VREF
COUNT /
T1./H/10409-4
NF.S. #5 256
N2 = 0
(N) has bath full-scale and zero errors
FIGURE 6. Transfer Function with
Zero and FulI-Scale Error
Auto-Zero and Full-Scale Features (Continued)
N'r.s.
Vin Vntr INPUT
N' = N - Nz TL/HM0409-5
N' has FulI-Scale Error
FIGURE 7. Transfer Functlons with
Zero-Correctlon Added
coo NT I
N''r.s.
TL/H/1(M09-6
(NES. - Nz)
FIGURE 8. Transfer Functlon with both Zero and
Fuil-Scaie Correction Added
N'=(N-Nz)x
Typical Applications
Application Suggestions and Formulae
1. The capacitor node impedance is approximately 30 p.11
and should have no parallel resistance for proper opera-
2. m when VIN = 0V will be finite (i.e., the comparator will
always toggle tor VIN 2 0V).
3. The ramp stop output is open collector, and an external
pull-up resistor is required.
4. All digital inputs and outputs are TTL compatible.
5. For proper operation. timing commences on the 0 to 1
transition of ramp start and terminates on the 1 to 0 tran-
sition of ramp stop.
6. u l M VREF (See Figure 1)
150pA-ln
. CH C
7. m (ramptlme) = Fn-TFC' tleax = T: y: VREF
(See Figure f)
Vcc - VREF
9. 2V S VREF S (Vcc - 2V)
10. Address lines A0, A1, A2 must be stable throughout the
sampling interval, u.
11. Pin 6 (REEF) should be bypassed to ground via a 0.02
“F capacitor.
8.in =
Mlcroprocessor Conttlderatlontt
Several alternatives exist from a hardware/sottware stand-
point in microprocessor based systems using the HA9708.
1.The ramp time measurement may be implemented in
software using a register increment followed by a branch
back depending on the status of the ramp stop.
2. Alternately, the ramp stop may be tied into the interrupt
structure in systems containing a programmable binary
timer. This scheme has the following advantages:
a. The CPU is not committed during the ramp time inter-
b. It requires only 4 bits of an I/O port for control signals.
3. The auto-zero/auto-full-scale (See Figures 5-6) should
use double precision, rounded (as opposed to truncated)
arithmatics. Several points are worth noting:
a. The subtractions are single op code instructions.
b. The full scale correction uses a multiply by 256 and
can be accomplished by a shift left 8 bits (usually one
instruction) or placing (N - N2) in the MSB register
and setting the LSB register to zero, for the double
precision divide.
c. The divisor (NFS, - N2) of the MSB register will al-
ways be zero.
These schemes have the following advantages:
a. No access to the data bus or address bus is required,
by the A/D system.
b. 4 IIO bits completely support the MD system.
c. Since auto full scale/auto zero are implemented in
software and long term drift (aging) effects are elimi-
nated.
d. Software overhead is minimal (typically 30 bytes).
ta. Where ratiometric operation is permissible, the 4 exter-
nal components may be t5% tolerance, including the
power supply.
Voc’ Vcco
"I lump
I2 coup
lil - u A3
_ Vcc’ it',, - I4 M9703 " l/O PORT
- 5 - Is At
Rt F, - 16 w
GNU REF
R2 -i— Ci'.
Note: AVI---
1:0. .02 pr -
(Approd Force) and can be Linearized (it necessary) in Software.
OUTPUT
TL/H/10409-11
FIGURE 9. Ratlotttetritt Strain Gage Sensore/Controller
BOLGV“
pA9708
Typical Applications (Continued)
SENSOR
llef Vcc+
sownou R3 I I
l n RAMP
PHOTO START
RESISTOR m - l2 cow
W RX 8 - l3 A3
Vcc’ E - " M9708 A2 I/O PORT
= g - l5 ht ht
1 RI Ct - l6 CAP
y I Cir.. CC l
REF GND REF B3 lo" C"'''"
R2 l 0.02 pF -
- I - CONTROL
r cmcuns
Applleatlorts
Beverage Brewers! Dispensers
Chemical Solution Control
Automatic Liquid Mixing Control
Ramp Current = IR = VCC(R1T1RZ) (k
I C,,,-')
RB) CC+
RampTi---v(i),-4)=z(c'?,-,,,)(1
FIGURE 10
TL/H/10409-12
+ 2) (CHRS)
This datasheet has been :
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This file is the datasheet for the following electronic components:
UA9708DC - product/ua9708dc?HQS=T|-nu|l-null-dscatalog-df—pf—null-wwe
UA9708DM - product/an708dm?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nulI-wwe
UA9708PC - product/ua9708pc?HQS=T|—nu|I-null-dscataIog-df-pf-null-wwe
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