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U404NLVishayN/a272avaiMonolithic N-Channel JFET Duals
U406NLVishayN/a25avaiMonolithic N-Channel JFET Duals


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U404NL-U406NL
Monolithic N-Channel JFET Duals
SST/U401NL Series
Vishay SiliconixNew Product
Monolithic N-Channel JFET Duals
SST404NLSST406NL U401NLU404NL U406NL

FEATURES BENEFITS APPLICATIONS Anti Latchup Capability Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: 2 pA Low Noise High CMRR: 102 dB External Substrate Bias—Avoids Latchup Tight Differential Match vs. Current Improved Op Amp Speed, Settling Time Accuracy Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signal Wideband Differential Amps High-Speed,Temp-Compensated,Single-Ended Input Amps High-Speed Comparators Impedance Converters
DESCRIPTION
The SST/U401NL series of high-performance monolithic dual
JFETs features extremely low noise, tight offset voltage andlow drift over temperature specifications, and is targeted foruse in a wide range of precision instrumentation applications.
This series has a wide selection of offset and driftspecifications with the U401NL featuring a 5-mV offset and
10-�V/�C drift.
Pins 4 and 8 of the SST series, and pin 4 of the U series part
numbers enable the substrate to be connected to a positive
polarity, external bias (VDD) to avoid latchup.
The U series, hermetically sealed TO-78 package is
available with full military processing. The SST series SO-8package provides ease of manufacturing, and the
symmetrical pinout prevents improper orientation. The SO-8package is available with tape-and-reel options for
compatibility with automatic assembly methods.
TO-78

Top ViewU401NLU404NLU406NL SUBSTRATE G2 D2
SUBSTRATE S2
Narrow Body SOIC

Top View
Marking Codes:
SST404NL - 404NLSST406NL - 406NL
CASE, SUBSTRATE
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage -40 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Current 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (1/16” from case for 10 sec.) 300�C. . . . . . . . . . . . . . . . . . .
Operating Junction Temperature -55 to 150�C. . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation : Per Sidea 300 mW. . . . . . . . . . . . . . . . . . . . . . . .
Totalb 500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
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