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Partno	Mfg	Dc	Qty	Available	Descript
TVP7000PZP	TI ?	N/a	45	avai	TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO AND GRAPHICS DIGITIZER WITH ANALOG PLL
TVP7000PZPR	TI	N/a	1557	avai	TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO AND GRAPHICS DIGITIZER WITH ANALOG PLL

TVP7000PZPR ,TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO AND GRAPHICS DIGITIZER WITH ANALOG PLLFEATURES APPLICATIONS• LCD TV/Monitors/Projectors• Analog Channels• DLP TV/Projectors– -6 dB to 6 d ..
TVP7001PZP ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70SLES164–FEBBRUARY 2006TERMINAL ASSIGNMENTSSOGIN_1 1 75 SDAGIN_1 2 74 SCLA18GND 3 73 I2CAA18VDD 4 72 ..
TVP7001PZPR ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70BLOCK DIAGRAMRIN_110−bitClamp PGARIN_2ADCRIN_3ROUT[9:0]GIN_1GIN_2 10−bit OutputClamp PGAADC Formatt ..
TVP7002PZP ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70 SLES206C –MAY 2007–REVISED APRIL 2013Terminal AssignmentsSOGIN_1 1 75 SDAGIN_1 2 74 SCL73AGND 3 I2 ..
TVP7002PZP ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog- ..
TVP7002PZPR ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70FEATURES23• Analog Channels • Output Formatter– –6-dB to 6-dB Analog Gain – Supports 20-bit 4:2:2 O ..
UC3845NG4 ,Current-Mode PWM Controller 8-PDIP 0 to 70Block Diagrams. 11Information..... 368.3 Feature Description.... 124 Revision HistoryChanges from R ..
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UC3845P , Current Mode PWM Controller
UC3845T ,HIGH PERFORMANCE CURRENT MODE PWM CONTROLLERELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for0 < T ..
UC3845T ,HIGH PERFORMANCE CURRENT MODE PWM CONTROLLERUC3842T UC3843TUC3844T UC3845T® HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER. TRIMMED OSCILLATOR FO ..
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TVP7000PZP-TVP7000PZPR
TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO AND GRAPHICS DIGITIZER WITH ANALOG PLL
www.ti.com
FEATURES APPLICATIONS
DESCRIPTION
TVP7000
SLES143–SEPTEMBER 2005
TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL LCD TV/Monitors/Projectors• Analog Channels DLP TV/Projectors–-6 dBto6 dB Analog Gain PDP TV/Monitors– Analog Input MUXs • PCTV Set-Top Boxes– Auto Video Clamp • Digital Image Processing– Three Digitizing Channels, Each With • Video Capture/Video EditingIndependently Controllable Clamp, PGA, • Scan Rate/Image Resolution Convertersand ADC Video Conferencing– Clamping: Selectable Clamping Between • Video/Graphics Digitizing EquipmentBottom Level and Mid-level Offset: 1024-Step Programmable RGBor
YPbPr Offset Control
TVP7000isa complete solution for digitizing video– PGA: 8-Bit Programmable Gain Amplifier and graphic signalsin RGBor YPbPr color spaces.– ADC: 8/10-Bit 150/110 MSPS A/D Converter The device supports pixel rates up to 150 MHz.– Automatic Level Control Circuit Therefore,it can be used for PC graphics digitizingto the VESA standardof SXGA (1280× 1024)– Composite Sync: Integrated Sync-on-Green
resolutionat 75 Hz screen refresh rate, andin videoExtraction From GreenLuminance Channel environments for the digitizingof digital TV formats,– Support for DC and AC-Coupled Input including HDTV upto 1080p. TVP7000 can be usedSignals to digitize CVBS and S-Video signal with 10-bit• PLL ADCs. Fully Integrated Analog PLL for Pixel Clock The TVP7000is powered from 3.3-V and 1.8-VGeneration supply and integratesa triple high-performance A/D
converter with clamping functions and variable gain,– 12-150 MHz Pixel Clock Generation From
independently programmable for each channel. TheHSYNC Input clamping timing windowis provided by an external– Adjustable PLL Loop Bandwidth for pulseor can be generated internally. The TVP7000Minimum Jitter includes analog slicing circuitryon theYorG inputto– 5-Bit Programmable Subpixel Accurate support sync-on-luminanceor sync-on-green extrac-
Positioningof Sampling Phase tion. In addition, TVP7000 can extract discrete
HSYNC and VSYNC from composite sync usinga• Output Formatter sync slicer.– Support for RGB/YCbCr 4:4:4 and YCbCr
TVP7000 also containsa complete analog PLL block4:2:2 Output Modesto Reduce Board Traces generatea pixel clock from the HSYNC input. Pixel– Dedicated DATACLK Output for Easy clock output frequencies range from 12 MHzto 150Latchingof Output Data MHz. All programmingof the partis done via an indus- Normal/FastI2C Interface try-standardI2C interface, which supports both read- Register Capability