TUA6024-2 ,2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-AmplifierWireless Components2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-AmplifierTUA6024-2 Version ..
TUA6030 ,Analog Terrestrial _ Cable Tuner SystemsWireless Components3-Band TV Tuner ICTUA6030, TUA6032 Version 2.1Specification July 2001 Revision ..
TUA6034T ,Digital Terrestrial Tuner _ Frontend SystemsWireless Components3-Band Digital TV / Set-Top-Box Tuner ICTUA6034, TUA6036 ’TAIFUN’ Version 2.4Sp ..
TUA6034-T ,Digital Terrestrial Tuner _ Frontend SystemsWireless Components3-Band Digital TV / Set-Top-Box Tuner ICTUA6034, TUA6036 ’TAIFUN’ Version 2.4Sp ..
TUA6034V ,3-Band Digital TV / Set-Top-Box Tuner ICSpecification, V 2.5, April 2004TUA6034, TUA60363-Band Digital TV / Set-Top-Box Tuner ICTAIFUNVersi ..
TUA6034V ,3-Band Digital TV / Set-Top-Box Tuner ICSpecification, V 2.5, April 2004TUA6034, TUA60363-Band Digital TV / Set-Top-Box Tuner ICTAIFUNVersi ..
UC3842BN ,HIGH PERFORMANCE CURRENT MODE PWM CONTROLLEROrder this document by UC3842B/D** ** * ** * * **HIGH PERFORMANCEThe UC3842B, UC3843B series are h ..
UC3842BNG , High Performance Current Mode Controllers
UC3842BVD ,HIGH PERFORMANCE CURRENT MODE CONTROLLERSfeatures consisting of input and referencePLASTIC PACKAGE8undervoltage lockouts each with hysteresi ..
UC3842BVD ,HIGH PERFORMANCE CURRENT MODE CONTROLLERSMAXIMUM RATINGSRating Symbol Value UnitTotal Power Supply and Zener Current (I + I ) 30 mACC ZOutpu ..
UC3842BVD ,HIGH PERFORMANCE CURRENT MODE CONTROLLERSELECTRICAL CHARACTERISTICS (V = 15 V [Note 2], R = 10 k, C = 3.3 nF. For typical values T = 25°C, f ..
UC3842D ,SMPS ControllerMaximum Ratings.. 612 Device and Documentation Support........ 357.2 ESD Ratings........ 612.1 Rela ..
TUA6024-2
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier
Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier
TUA6024-2 Version 2.0
Specification July 2001
Edition 12.99
Published by Infineon Technologies AG
Balanstraße 73,
81541 München© InfineonTechnologiesAG 15.01.03.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits im-
plemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest
InfineonTechnologies Office.
InfineonTechnologiesAG is an approved CECC manufacturer.
PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing
material back, if it is sorted. You must bear the costs of transport.
Product Info
Product Info
General DescriptionThe TUA6024-2 is a 5 V mixer/oscilla-
tor and synthesizer for TV and VCR
tuners.
FeaturesGeneralSuitable for analog tuners and for
digital CATV tunersCompatible with TUA6024-S and
TUA6024-K in normal modeNew features in extended modeFull ESD protection
Mixer/OscillatorHigh impedance mixer input for
LOW/MID bandLow impedance mixer input for
HIGH band4 pin oscillator for LOW/MID band4 pin oscillator for HIGH band
IF-Amplifierbalanced SAW preamplifier Low output impedance
PLLPLL with short lock-in timeHigh voltage VCO tuning outputFast I2C bus3 NPN bandswitch buffersInternal LOW-MID/HIGH switchLock-in flagPower-down reset4 programmable reference divider
ratios: 24, 64, 80, 128 4 programmable charge pump cur-
rents
Application
Ordering InformationThe IC is suitable for PAL tuners in TV- and VCR-sets or CATV set-top
receivers for analog TV and digital cable TV.
Table of ContentsTable of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12.1General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.3Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.4Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.2Internal Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.3Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.4Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14.1Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.2Evaluation board, low phase noise application. . . . . . . . . . . . . . . . . .4-3
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15.1Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.1.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.1.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
5.1.3AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
5.2Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
5.3I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14
5.4Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15
5.4.1Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . .5-15
5.4.2Gain (GV) test Set-up in HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15
5.4.3Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . .5-16
5.4.4Noise Figure Test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . .5-16
5.4.5Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . .5-17
5.4.6Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . .5-17
5.4.7Cross modulation Test Set-up in HIGH band. . . . . . . . . . . . . . . . . .5-18
5.4.8Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18
5.5Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-19
5.5.1Input admittance (S11) of the LOW/MID band mixer input. . . . . . . .5-19
5.5.2Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . .5-19
5.5.3Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . .5-20
5.5.4Output impedance (S22) of the IF output. . . . . . . . . . . . . . . . . . . . .5-20
Product Description2.1General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.3Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.4Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Product Description
2.1General DescriptionThe TUA6024-2 device combines a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscilla-
tors for use in TV and VCR tuners.
The PLL block with four selectable chip addresses forms a digitally programm-
able phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise
setting of the frequency of the tuner oscillator up to 1024 MHz in increments of
31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a micropro-
cessor via an I2C bus. The device has three output ports. A flag is set when the
loop is locked. It can be read by the processor via the I2C bus.
The mixer-oscillator block includes two balanced mixers (one mixer with high-
impedance input and one mixer with a balanced low-impedance input), two fre-
quency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an
IF amplifier, a low-noise reference voltage source, and a band switch.
2.2Features
GeneralSuitable for analog tuners and for digital CATV tunersCompatible with TUA6024-S and TUA6024-K in normal modeNew features in extended modeFull ESD protection
Mixer/OscillatorHigh impedance mixer input for LOW/MID bandLow impedance mixer input for HIGH band4 pin oscillator for LOW/MID band4 pin oscillator for HIGH band
IF-Amplifierbalanced SAW preamplifier Low output impedance
PLLPLL with short lock-in timeHigh voltage VCO tuning outputFast I2C bus3 NPN bandswitch buffersInternal LOW-MID/HIGH switch
Product DescriptionLock-in flagPower-down reset4 programmable reference divider ratios: 24, 64, 80, 128 4 programmable charge pump currents
2.3Application
Functional Description3.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.2Internal Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.3Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.4Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.1General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.2Mixer-Oscillator block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.3PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.4I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
Functional Description
3.1Pin ConfigurationTUA6024-2_pin_config
Figure 3-1Pin Configuration
Functional Description
3.2Internal Pin Configuration
Functional Description
Functional Description
Functional Description
Functional Description
3.3Block DiagramBlock_diag
Figure 3-2Block Diagram
Functional Description
3.4Circuit Description
3.4.1GeneralIn the normal mode (see Table 5-7 Test modes on page 31) the IC is compatible with
TUA6024-S and TUA6024-K. An extended mode makes a reference divider
ratio of 24 (see Table 5-8 Reference divider ratio on page 31) and two additional charge
pump currents (see Table 5-9 Charge pump current on page 32) available.
3.4.2Mixer-Oscillator blockThe mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for LOW and / or MID band and HIGH band, an
IF amplifier, a reference voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switching in the tuner front-end is done by using two or three
port outputs. In the selected band the signal passes a tuner input stage with
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the bal-
anced mixer input of the IC which has in case of LOW / MID a high-impedance
input and in case of HIGH a low-impedance input. The input signal is mixed
there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced high-impedance output pair by means of a
parallel tuned circuit. The following SAW preamplifier has a low output imped-
ance to drive the SAW filter directly.
3.4.3PLL blockThe oscillator signal is internally DC-coupled as a differential signal to the pro-
grammable divider inputs. The signal subsequently passes through a program-
mable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency / phase detector to a reference frequency fref = 31.25, 50, 62.5 or
166.7 kHz.This frequency is derived from an unbalanced, low-impedance 4
MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.
The phase detector has two outputs that drive two current sources of opposite
polarity as charge pump. If the negative edge of the divided VCO signal appears
prior to the negative edge of the reference signal, the positive current source
pulses for the duration of the phase difference. In the reverse case the negative
current source pulses. If the two signals are in phase, the charge pump output
(CP) goes into the high-impedance state (PLL is locked). An active low-pass fil-
ter integrates the current pulses to generate the tuning voltage for the VCO
(internal amplifier, external pull-up resistor at TUNE and external RC circuitry).
The charge pump output is also switched into the high-impedance state if the
Functional Descriptioncontrol bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of
self-discharge in the peripheral circuitry. TUNE may be switched off by the con-
trol bit OS to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V .
By means of the control bits CP, CM, T0 and T1 the pump current can be
switched between four values by software. This programmability permits alter-
ation of the control response time of the PLL in the locked-in state. In this way
different VCO gains can be compensated, for example.
The software-switched ports PLOW, PMID and PHIGH are general-purpose
open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test signals
fref (i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID respec-
tively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL
= 1, the maximum deviation of the input frequency from the programmed fre-
quency is given by
Δf = ± IP (KVCO / fXTAL) (C1+C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscil-
lator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-2 Evalu-
ation Board, low phase noise application on page 20). As the charge pump pulses at i.e. 62.5
kHz (= fref), it takes a maximum of 16 μs for FL to be reset after the loop has lost
lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive fref periods. Therefore it takes between 128 and
144 μs for FL to be set after the loop regains lock.
3.4.4I2C-Bus InterfaceData is exchanged between the processor and the PLL via the I2C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table ”Bit Allocation” (see Table 5-4 Bit Allocation Read / Write on page 30) should be
referred to the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA
Functional Descriptionline to LOW (acknowledge condition). The first byte is comprised of seven
address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 31).
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset
at the end of a READ operation.
Applications4.1Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.2Evaluation board, low phase noise application. . . . . . . . . . . . . . . . . .4-3
Applications
4.1Evaluation board, PAL applicationTUA6024-2_application-circuit
Figure 4-1Evaluation Board, PAL application
Applications
4.2Evaluation board, low phase noise applicationTUA6024-2_application-circuit
Figure 4-2Evaluation Board, low phase noise application
