TUA6010XS ,TV Mixer-Oscillator-PLLapplications, processes and circuits im-plemented within components or assemblies.The information d ..
TUA6010XS ,TV Mixer-Oscillator-PLLcharacteristics.Terms of delivery and rights to change design reserved.Due to technical requirement ..
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TUA6010XS ,TV Mixer-Oscillator-PLLGeneral Description The TUA 6010XS device combines a digitally programmable phase locked loop (PLL) ..
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TUA6010XS-TUA6010XS ..
TV Mixer-Oscillator-PLL
Wireless Components
TV Mixer-Oscillator-PLL
TUA 6010XS Version 1.0
Specification August 1999
Edition 03.99
Published by Infineon Technologies AG i. Gr.,
SC,
Balanstraße 73,
81541 München© InfineonTechnologiesAG i.Gr. 24.08.99.
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Product Info
Product Info
General DescriptionThe TUA 6010XS device combines a
digitally programmable phase locked
loop (PLL), with a mixer-oscillator block
including two balanced mixers and
oscillators for use in TV tuners.
Features�PLL with short lock-in time; no
asynchronous divider stageFast I2C bus mode possible4 programmable chip addressesShort pull-in time for quick channel
access and optimized loop stability3 high-current switch outputs 2 TTL inputs5-level A/D converterLock-in flagPower-down flagFew external componentsFrequency and amplitude-stable
balanced oscillator for the VHF,
HYPER and UHF frequency rangeOptimum decoupling of input
frequency from oscillatorDouble balanced mixer with wide
dynamic range and low-impedance
inputs for the VHF, HYPER and
UHF frequency range Internal band switchInternal low-noise reference volt-
age sourcePackage TSSOP 28Full ESD protection
Application�The IC is suitable for all tuners in
TV- and VCR-sets or cable set-top
receivers for analog TV an Digital
Ordering Information
Table of ContentsTable of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12.1Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.3Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.4Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.2Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.3Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.4Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.1Mixer-Oscillator block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.2PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.3I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.2Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.1Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.1.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.1.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5.1.3AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
5.2Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8
5.3I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
5.4Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11
Product Description2.1Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.3Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.4Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Product Description
2.1OverviewThe TUA 6010XS device combines a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscilla-
tors for use in TV tuners.
The PLL block with four hard-switched chip addresses forms a digitally pro-
grammable phase locked loop. With a 4 MHz quartz crystal, the PLL permits
precise setting of the frequency of the tuner oscillator up to 900 MHz in incre-
ments of 62.5 kHz. The tuning process is controlled by a microprocessor via an 2C bus. The device has three output ports, which all can also be used as input
ports (two TTL inputs and one A/D converter input). A flag is set when the loop
is locked. The input ports and lock flag can be read by the processor via the I2C
bus. The mixer-oscillator block includes two balanced mixers (double balanced
mixer with low-impedance input), two frequency and amplitude-stable balanced
oscillators for VHF, HYPER and UHF, a low-noise reference voltage source and
a band switch.
2.2FeaturesPLL with short lock-in time; no asynchronous divider stageFast I2C bus mode possible4 programmable chip addressesShort pull-in time for quick channel access and optimized loop stability3 high-current switch outputs 2 TTL inputs5-level A/D converterLock-in flagPower-down flagFew external componentsFrequency and amplitude-stable balanced oscillator for the VHF, HYPER
and UHF frequency rangeOptimum decoupling of input frequency from oscillatorDouble balanced mixer with wide dynamic range and low-impedance inputs
for the VHF, HYPER and UHF frequency range Internal band switchInternal low-noise reference voltage sourcePackage TSSOP 28Full ESD protection
Product Description
2.3ApplicationThe IC is suitable for all tuners in TV- and VCR-sets or cable set-top
2.4
Functional Description3.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.2Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.3Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.4Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
Functional Description
3.1Pin ConfigurationPin_config.wmf
Figure 3-1Pin Configuration
Functional Description
3.2Pin Definition and Function
Functional Description
Functional Description
Functional Description
Functional Description
3.3Block DiagramFigure 3-2Block Diagram
VCCACAS
IFo
GND
VCCD
SDA
Functional Description
3.4Circuit Description
3.4.1Mixer-Oscillator blockThe mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for VHF and/or HYPER and UHF, a reference
voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switch ensures that only one mixer-oscillator block at a time
is activated. In the activated band the signal passes a frontend stage with MOS-
FET amplifier, a double-tuned bandpass filter and is then fed to the balanced
mixer input of the IC which has a low-impedance input.
The input signal is mixed there with the on chip oscillator signal from the acti-
vated oscillator section.
3.4.2PLL blockThe mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential
signal at the programmable divider inputs. The signal subsequently passes
through a programmable divider with ratio N = 256 through 32767 and is then
compared in a digital frequency / phase detector to a reference frequency
fref = 62.5 kHz.
This frequency is derived from a balanced, low-impedance 4 MHz crystal oscil-
lator (pin Q, Qx) divided by Q = 64.
The phase detector has two outputs UP and DOWN that drive two current
sources I+ and I- of a charge pump. If the negative edge of the divided VCO sig-
nal appears prior to the negative edge of the reference signal, the I+ current
source pulses for the duration of the phase difference. In the reverse case the
I- current source pulses. If the two signals are in phase, the charge pump output
(CHGPMP) goes into the high-impedance state (PLL is locked). An active low-
pass filter integrates the current pulses to generate the tuning voltage for the
VCO (internal amplifier, external pullup resistor at TUNE and external RC cir-
cuitry). The charge pump output is also switched into the high-impedance state
when the control bit T0 = 1. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of
self-discharge in the peripheral circuity. TUNE may be switched off by the con-
trol bit OS to allow external adjustments.
When the VCO is not working the PLL locks to a tuning voltage of 33V.
By means of control bit 5I the pump current can be switched between two val-
ues by software. This programmability permits alteration of the control response
of the PLL in the locked-in state. In this way different VCO gains can be com-
pensated, for example.
Functional DescriptionThe software-switched ports P0, P1, P2 are general-purpose open-collector
outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / 64) and Cy
(divided input signal) to P0 and P1 respectively. P0, P1, P2 are bidirectional.
The lock detector resets the lock flag FL when the width of the charge pump cur-
rent pulses is greater than the period of the crystal oscillator (i.e. 250 ns).
Hence, when FL = 1, the maximum deviation of the input frequency from the
programmed frequency is given by
Δf = ± IP (KVCO / fQ) (C1+C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscilla-
tor frequency and C1, C2 the capacitances in the loop filter (see application cir-
cuit). As the charge pump pulses at 62.5 kHz (= fref), it takes a maximum of
16 μs for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive fref periods. Therefore it takes between 128 and
144 μs for FL to be set after the loop regains lock.
3.4.3I2C-Bus InterfaceData is exchanged between the processor and the PLL via the I2C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table 1 ”bit allocation” should be referred to the following description. All
telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during
which the control logic returns the SDA line to LOW (acknowledge condition).
The first byte is comprised of seven address bits. These are used by the pro-
cessor to select the PLL from several peripheral components (chip select). The
LSB bit (R/W) determines whether data are written into (R/W = 0) or read from
(R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
