TSB43CA42GGW ,TSB43CA42 iceLynx-Micro 2 Port IEEE 1394a-2000 CES Abbrev. DM15-Apr-2017PACKAGING INFORMATIONOrderable Device Status Package Type Package Pins Package Eco Plan ..
TSB43CA42ZGW ,TSB43CA42 iceLynx-Micro 2 Port IEEE 1394a-2000 CES Abbrev. DMfeatures an embedded ARM7TDMI microprocessor core with access to 256K bytes of internalprogram memo ..
TSB43CB43APGFG4 ,iceLynx Micro with Streaming Audio 176-LQFP -20 to 70/productcontent for the latest availabilityinformation and additional product content details.TBD: ..
TSB43DA42 ,IEC61883, 1394a Link Layer Controller integrated with a 1394a, 400Mbps, 2-port Physical Layer (PHY)SLLS560–FEBRUARY 2007DESCRIPTION/ORDERING INFORMATIONThe TSB43DA42/TSB43DB42 are high-performance c ..
TSB43DA42AGHC , IEEE 1394a-2000 CONSUMER ELECTRONICS SOLUTION
TSB43DA42AZHC ,IEC61883, 1394a Link Layer Controller integrated with a 1394a, 400Mbps, 2-port Physical Layer (PHY) 196-BGA MICROSTAR -20 to 85SLLS560–FEBRUARY 2007APPLICATION INFORMATIONHDTV ApplicationSDRAM CPUTSB43DA42 Audio DACMPEG2 Trans ..
UC1517J/883B , Stepper Motor Drive Circuit
UC1517J/883B , Stepper Motor Drive Circuit
UC1524 ,Advanced Regulating Pulse Width Modulators
UC1524AJ ,Advanced Regulating Pulse Width ModulatorsFEATURESFully Interchangeable withStandard UC1524 FamilyPrecision Reference InternallyTrimmed to i1 ..
UC1524J/883B ,Advanced Regulating Pulse Width Modulators
UC1524J/883B ,Advanced Regulating Pulse Width Modulators
TSB43CA42-TSB43CA42GGW-TSB43CA42ZGW
TSB43CA42 iceLynx-Micro 2 Port IEEE 1394a-2000 CES Abbrev. DM
www.ti.com
FEATURES
TSB43CA43A
TSB43CB43A
TSB43CA42
SLLA211–JUNE 2006
iceLynx-Micro IEEE 1394a-2000 Consumer Electronics Solution Internal ARM7 1394 Features – 50-MHz operating frequency Integrated 400 Mbps 3-port PHY – 32-bit and thumb (16-bit) mode support Compliant with IEEE 1394-1995 and IEEE – UART included for communication
1394a-2000 standards – 256K bytesof program memory included on Supports bus manager functions and chip
automatic 1394 self-ID verification. – ARM JTAG included for software debug Separate Async Ack FIFO decreases the •
Data Buffers
ack-tracking burden on in-CPU and ex-CPU – Large 16.5K byte total FIFO•
DTLA Encryption Support for MPEG2-DVB, – Programmable data/space availableDSS, DV, and Audio (TSB43CA43A and indicators for buffer flow controlTSB43CA42 Only) •
Hardware Packet Formatting for the– Two M6 baseline ciphers (one per HSDI Following Standardsport) – DVB MPEG2 transport stream (IEC61883-4)•
Content key generation from exchange – DSS MPEG2 transport stream per standardkey – DV Stream (IEC 61883-2) SD-DV– AKE acceleration featuresin hardware Audio over 1394 (IEC 61883-6)•
Random Number Generator – Audio Music Protocol (version 1.0 and•
Secure Hash Algorithm, Revision1 enhancements)(SHA-1) Asynchronous and asynchronous stream– Other AKE acceleration features (as defined by IEEE 1394)•
Elliptical curve digital signature algorithm •
Additional Features(EC-DCA) both signature and verification – PID filtering for transmit function (upto16•
Elliptical curve Diffie-Hellman (EC-DH), separate PIDs per HSDI)first phase value and shared secret Packet insertion– two insertion buffers percalculation
HSDI•
160-bit math functions –11 general-purpose inputs/outputs (GPIOs)•
High Speed Data Interface (HSDI) Interrupt drivento minimize CPU polling.– Two configurable high speed data Single 3.3-V supplyinterfaces support the following audio and
video modes: – JTAG interfaceto support post-assembly
scanof device I/O– boundary scan•
MPEG2-DVB interface MPEG2-DSS interface DV codec interface IEC60958 interface DAC interface SACD interface 16-bit parallel synchronous memory type
