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TSB43AB22-TSB43AB22PDT
OHCI 1.1, 1394a Link Layer Controller integrated with a 1394a, 400Mbps, 2-port Physical Layer (PHY)
www.ti.com
FEATURESNot Recommendedfor New Designs
TSB43AB22
SLLA208–JUNE 2006
Integrated 1394a-2000 OHCI PHY/Link-Layer Controller PHY-Link logic performs system initialization
and arbitration functions•
Fully compliant with provisionsof IEEE Std
1394-1995 fora high-performance serial bus1 •
PHY-Link encode and decode functions
and IEEE Std 1394a-2000 included for data-strobe bit level encoding Fully interoperable with FireWire and i.LINK •
PHY-Link incoming data resynchronizedto
implementationsof IEEE Std 1394 local clock Compliant with Intel Mobile Power Guideline •
Low-cost 24.576-MHz crystal provides
2000 transmit and receive dataat 100M bits/s,
200M bits/s, and 400M bits/s•
Full IEEE Std 1394a-2000 support includes:
connection debounce, arbitrated short reset, •
Node power class information signaling for
multispeed concatenation, arbitration system power management
acceleration, fly-by concatenation, and port •
Serial ROM interface supports 2-wire serialdisable/suspend/resume EEPROM devices Power-down featuresto conserve energyin •
Two general-purpose I/Os
battery-powered applications include: •
Register bits give software controlofautomatic device power down during contender bit, power class bits, link activesuspend, PCI power management for control bit, and IEEE Std 1394a-2000 featureslink-layer, and inactive ports powered down •
Fabricatedin advanced low-power CMOS•
Ultralow-power sleep mode process•
Two IEEE Std 1394a-2000 fully compliant •
PCI and CardBus register supportcable portsat 100M bits/s, 200M bits/s, and •
Isochronous receive dual-buffer mode400M bits/s •
Out-of-order pipelining for asynchronous•
Cable ports monitor line conditions for active transmit requestsconnectionto remote node •
Register access fail interrupt when the PHY•
Cable power presence monitoring SCLKis not active•
Separate cable bias (TPBIAS) for each port •
PCI power-management D0, D1, D2, and D3•
1.8-V core logic with universal PCI interfaces power statescompatible with 3.3-V and 5-V PCI signaling •
Initial bandwidth available and initialenvironments channels available registers•
Physical write postingof upto three •
PME support per 1394 Open Host Controlleroutstanding transactions Interface Specification•
PCI burst transfers and deep FIFOstoNOTE: Implements technology coveredby oneor more patents
tolerate large host latency of Apple Computer, Incorporated and SGS Thompson,
Limited.•
PCI_CLKRUN protocol External cycle timer control for customized
synchronization Extended resume signaling for compatibility DV components
