TSB43AA82APGE ,2 Port High Performance Integrated Phy and Link Layer Chip for PC PeripheralsFEATURES • Data Transfers:• IEEE 1394a-2000 Compliant – Auto Address Increment of Direct/IndirectAd ..
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TSB43AA82A-TSB43AA82APGE
2 Port High Performance Integrated Phy and Link Layer Chip for PC Peripherals
www.ti.com
FEATURES
DESCRIPTION
TSB43AA82A
TSB43AA82AI
SLLA205–MAY 2006
(iSphynxII) 1394 Integrated PHY and Link-Layer Controller
for SBP-2 Products and DPP Products Data Transfers: IEEE 1394a-2000 Compliant – Auto Address Incrementof Direct/Indirect
Addressing on Data Transfer (Packetizer)•
Single 3.3-V Supply Automated Header Insert/Strip for DMA•
Internal 1.8-V Circuitto Reduce Power Data TransfersConsumption 8-/16-Bit Asynchronous and Synchronous•
Integrated 400-Mbps Two-Port Physical Layer
DMA I/F With Handshake and Burst Mode(PHY) Supports ATAPI (Ultra-DMA) Mode and•
Internal Voltage Regulator SCSI Mode•
IEEE 1394 Related Functions: 8-/16-Bit Data/Address Multiplex– Automated Read Response for ConfigROM Microcontroller and 8-/16-Bit SeparatedRegister Access Data/Address Bus– Automated Single Retry Protocol and Split – Three FIFO Configurations That SupportTransaction Control High Performance for the DMA and for•
SBP-2 Related Functions: Command Exchanges Supports Four Initiators by Automated •
Asynchronous Command FIFO: 1512Transactions and More Can Be Supported BytesThrough Firmware. •
Config ROM/LOG FIFO: 504 Bytes– Automated Management ORB Fetching •
DMA FIFO: 4728 Bytes– Automated Linked Command ORB Fetching Automated PageTable Fetching Automated Status Block Transmit Abilityto Support Direct Print Protocol (DPP)
ModeThe TSB43AA82Aisa high performance 1394 integrated PHY and link layer controller.Itis compliant with the
IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers.
TSB43AA82A hasa generic 16-/8-bit host bus interface.It supports parallelor multiplexed connectionsto the
microcontroller (MCU)at ratesupto40 MHz.
The TSB43AA82A offers large data transfers with three mutually independent FIFOs:1) the asynchronous
command FIFO with 1512 Bytes,2) the DMA FIFO with 4728 bytes and3) the Config ROM/LOG FIFO with 504
bytes.
The featuresof the TSB43AA82A support the serial bus protocol2 (SBP-2).It handlesupto four initiators with transaction/timer manager. This SBP-2 transaction engine supports fully automated operation request fetches and fully automated memory page table fetches for both read and write transactions. responses node requests are provided; this includes respondingto another node’s read
