TSB41LV06APZP ,IEEE 1394a Six-Port Cable Transceiver/Arbiter SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000 ..
TSB41LV06APZP ,IEEE 1394a Six-Port Cable Transceiver/ArbiterFeatures Fully Interoperable With FireWire and Data Interface to Link-Layer Controlleri.LINK I ..
TSB42AA4 ,1394 Link Layer Controller With DTCP Content Protection for Consumer Electronics Applications
TSB42AA4 ,1394 Link Layer Controller With DTCP Content Protection for Consumer Electronics Applications
TSB42AA4 ,1394 Link Layer Controller With DTCP Content Protection for Consumer Electronics Applications
TSB42AA9PZT ,High-Performance 1394 Link-Layer Controller for ATAPI/ATA Storage Products
UC-0.5 , P-Clips
UC1517J/883B , Stepper Motor Drive Circuit
UC1517J/883B , Stepper Motor Drive Circuit
UC1524 ,Advanced Regulating Pulse Width Modulators
UC1524AJ ,Advanced Regulating Pulse Width ModulatorsFEATURESFully Interchangeable withStandard UC1524 FamilyPrecision Reference InternallyTrimmed to i1 ..
UC1524J/883B ,Advanced Regulating Pulse Width Modulators
TSB41LV06A-TSB41LV06APZP
IEEE 1394a Six-Port Cable Transceiver/Arbiter
Fully Compliant With OpenHCIRequirements Provides Six P1394a Fully Compliant Cable
Ports at 100/200/400 Megabits per Second
(Mbits/s) Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume Extended Resume Signaling for
Compatibility With Legacy DV Devices Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Terminal,
Link Interface Disable via LPS, and Inactive
Ports Powered-Down Ultralow-Power Sleep Mode Node Power Class Information Signaling
for System Power Management Cable Power Presence Monitoring Cable Ports Monitor Line Conditions for
Active Connection to Remote Node Interface to Link Layer Controller Supports
Low Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation Interoperable With Link-Layer Controllers
Using 3.3 V and 5 V Supplies Interoperable With Other Physical Layers
(PHYs) Using 3.3 V and 5 V Supplies Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz Incoming Data Resynchronized to Local
Clock Logic Performs System Initialization and
Arbitration Functions Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding Separate Cable Bias (TPBIAS) for Each Port Single 3.3-V Supply Operation Low Cost High Performance 100-Pin TQFP
(PZP) Thermally Enhanced Package Direct Drop-In Upgrade for TSB41LV06PZP
descriptionThe TSB41LV06A provides the digital and analog transceiver functions needed to implement a six-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV06A is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12LV01A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
