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TSB14AA1A-TSB14AA1AIPFB
IEEE 1394-1995, 3.3V, 1-port, 50/100Mbps, Backplane PHY
www.ti.com
FEATURES
DESCRIPTION
TSB14AA1A
TSB14AA1AI
TSB14AA1AT
SLLA222–JUNE 2006
3.3-V IEEE 1394-1995 Backplane PHY Logic Performs System Initialization
Arbitration Functions. Encode And Decode•
Providesa Backplane 1394 Environment That
Functions Included for Data-Strobe Bit LevelSupports an Asynchronous Transfer Rateof
Encoding. Incoming Data Resynchronizedto50or 100 Mbits/s Across2 Etches
Local Clock.•
Single 3.3-V Supply Operation With 5-V •
Operates Over the Extended TemperatureTolerance on the Transceiver Receive
Rangesof 0°Cto 70°C (no suffix), –40°CtoInterface
85°C(I suffix), and –40°Cto 105°C(T suffix)•
Allows Utilizationof 3-State Driversas Well •
Packagedin the Very Compact 48-Pin7x7xas Open-Collector Drivers 1 mm PFB Package•
Software Compatible With the TSB14CO1APM(1) IEEE Std 1394a–2000, IEEE Standardfora High•
Enhanced Compatibility With the 1394 Cable Performance Serial Bus– Amendment1
Link Layer. Compatible With 1394–1995 and (2) IEEE Std 1394–1995, IEEE Standardfora High Performance
1394a–2000 Link Layers; PHY/link Interfaceis Serial Bus
1394a Compliant1(3) Implements technology coveredby oneor more patentsof•
Supports Provisionsof IEEE 1394–199523 Apple Computer, Inc. andST Microelectronics.
Extensive Testability and Debug Functions
Added. Expanded Register Set Including
Automatic SavingofID and Priority for Last
Node Winning Arbitration 100 MHzor50 MHz Oscillator Provides
Transmit, Receive Data, and Link Layer
Controller (LLC) ClocksThe TSB14AA1A (TSB14AA1A referstoall three devices: TSB14AA1A, TSB14AA1AI, and TSB14AA1AT)is the
second-generation 1394 backplane physical layer device.Itis recommended for useinall new designs instead the first generation TSB14C01A.It provides the physical layer functions neededto implementa single port
nodeina backplane based 1394 network. The TSB14AA1A provides two pins for transmitting, two for receiving,
and two pinsto externally control the transceivers for data and strobe.In additionto supporting open-collector
drivers, the TSB14AA1A can also support 3-state(1) (high-impedance) drivers. The TSB14AA1Ais not designed drive the backplane directly; this function must be provided externally. The TSB14AA1Ais designedto
interface witha link-layer controller (LLC), suchas the TSB12LV01B, TSB12LV32, TSB12LV21B, etc.
The TSB14AA1A requires an external 98.304-MHz reference oscillator input for S100 asynchronous only
operationor 49.152-MHz for S50 asynchronous only operation. Two clock select pins (CLK_SEL0, CLK_SEL1)
select the speed mode for the TSB14AA1A. For S100 operation, the 98.304-MHz reference signalis internally
dividedto provide the 49.152-MHz system clock signals usedto control transmissionof the outbound encoded
strobe and data information. The 49.152-MHz clock signalis also supplied to the associated LLC for
synchronizationof the two chips andis used for resynchronizationof the received data. For S50 operation,a reference signalis used. This reference signalis internally dividedto provide the 24.576-MHz signalsfor S50 operations.
