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TSB12LV32-TSB12LV32PZ
General-Purpose Link Layer Controller (GP2Lynx)
www.ti.com
FEATURES
DESCRIPTION
TSB12LV32
TSB12LV32I
SLLA215–JUNE 2006
IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller for
Computer Peripherals and Consumer Audio/Video Electronics Programmable Microcontroller Interface With
8-Bitor 16-Bit Data Bus, Multiple Modesof•
Compliant With IEEE 1394-1995 Standards
Operation Including Burst Mode, and Clockand 1394a-2000 Supplement for High
Frequencyto60 MHzPerformance Serial Bus1 8-Bitor 16-Bit Data-Mover Port (DM Port)•
Supports Transfer Ratesof 400, 200,or 100
Supports Isochronous, Asynchronous, andMbps
Asynchronous Streaming Transmit/Receive•
Compatible With Texas Instruments Physical From an Unbuffered Portata ClockLayer Controllers (Phys) Frequencyof25 MHz.•
Supports the Texas Instruments Bus Holder •
Backward Compatible With AllGalvanic Isolation Barrier TSB12LV31(GPLynx) Microcontroller and•
Glueless Interfaceto 68000 and ColdFire Data-Mover Functionalityin HardwareMicrocontrollers/Microprocessors •
Two-Channel Support for Isochronous•
Supports ColdFire Burst Transfers Receiveto Unbuffered 8/16 Data-Mover Port•
2-Kbyte General Receive FIFO (GRF) •
Four-Channel Support for IsochronousAccessed Through Microcontroller Interface Transmit From Unbufferred 8/16 BitSupports Asynchronous and Isochronous Data-Mover PortReceive. •
Single 3.3-V Supply Operation With 5-V•
2-Kbyte Asynchronous Transmit FIFO (ATF) Tolerance Using 5-V Bias TerminalsAccessed Through Microcontroller Interface •
High Performance 100-Pin PZ PackageSupports Asynchronous Transmissions.NOTE: Implements technology coveredby oneor more patents Apple Computer, Incorporated and SGS Thomson,
Limited.
The TSB12LV32 (GP2Lynx)isa high-performance general-purpose IEEE 1394a-2000 link-layer controller (LLC)
with the capabilityof transferring data between the 1394 Phy-link interface, an external host controller, and an
external device connectedto the data-mover port (local bus interface). The 1394 Phy-link interface provides the
connectiontoa 1394 physical layer device andis supported by the LLC. The LLC provides the control for
transmitting and receiving 1394 packet data between the microcontroller interface and the Phy-link interface via
internal 2-Kbyte FIFOsat rates upto 400 Mbps. The TSB12LV32 transmits and receives correctly formatted
1394 packets, generates and detects the 1394 cycle start packets, communicates transaction layer transmit
requeststo the Phy, and generates and inspects the 32-bit cyclic redundancy check (CRC).
The TSB12LV32is capableof being 1394 cycle master (CM), 1394 bus manager, 1394 isochronous resource
manager (IRM)if additional control status registers (CSRs) are added via the external host controller, and
supports receptionof 1394 isochronous data on two channels and transmissionof 1394 isochronous data on
four supports a direct interface to many microprocessors/microcontrollers by including endian TSB12LV32 hasa generic 16-/8-bit host bus interface which includes support