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TSB12LV26-TSB12LV26PZT
OHCI-Lynx PCI-Based IEEE 1394 Host Controller
www.ti.com
FEATURES
DESCRIPTION
TSB12LV26
TSB12LV26I
SLLA214–JUNE 2006
OHCI-Lynx™ PCI-Based IEEE 1394 Host Controller External cycle timer control for customized
synchronization•
3.3-V and 5-V PCI bus signaling PCI burst transfers and deep FIFOsto•
3.3-V supply (core voltageis internally
tolerate large host latencyregulatedto 1.8V) Two general-purpose I/Os•
Serial bus data ratesof 100M bits/s, 200M
bits/s, and 400M bits/s •
Fabricatedin advanced low-power CMOS
process•
Physical write postingof upto three
outstanding transactions •
Packagedin 100-terminal LQFP (PZT) Serial ROM interface supports 2-wire devices •
PCI_CLKRUN protocolThe Texas Instruments TSB12LV26 deviceisa PCI-to-1394 host controller compliant with the PCI Local Bus
Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host
Controller Interface Specification. The chip provides the IEEE 1394 link function andis compatible with 100M
bits/s, 200M bits/s, and 400M bits/s serial bus data rates. requiredby the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal
control registers are memory-mapped and nonprefetchable. The PCI configuration headeris accessed through
configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the
TSB12LV26 deviceis compliant with the PCI Bus Power Management Interface Specification, per the PC 99
Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting andis capableof transferringa cachelineof dataat
132M bytes/s after connectionto the memory controller. Since PCI latency can be large, deep FIFOs are
providedto buffer 1394 data.
The TSB12LV26 device provides physical write posting buffers anda highly-tuned physical data path for SBP-2
performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst
transfers, advanced internal arbitration, and bus-holding bufferson the PHY/link interface. advanced CMOS process achieves low power consumption and allows the TSB12LV26 deviceto operateat
PCI clock ratesupto33 MHz.
NOTE:This productis for high-volume PC applications only. Fora complete datasheetor
more information contact support.
