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TSB12LV21BPGF
PCILynx
www.ti.com
FEATURES
DESCRIPTION
TSB12LV21B
TSB12LV21BI
TSB12LV21BM
SLLA213–JUNE 2006
(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER Supports Plug-and-Play (PnP) Specification IEEE Standard for 1394-1995 Compliant •
Generates 32-bit CRC for Transmissionof
1394 Packets•
IEEE Standard for 1212-1991 Compliant Performs 32-bit CRC Checking on Reception•
Supports IEEE 1394-1995 Link Layer Control of 1394 Packets•
PCI Local Bus Specification Rev. 2.1 •
Provides PCI Bus Master Function forCompliant
Supporting DMA Operations•
Supports IEEE 1394 Transfer Ratesof 100, •
Provides PCI Slave Function for Read/Write200, and 400 Mb per Second Accessof Internal Registers•
3.3-V Core Logic While Maintaining 5-V •
Supports Distributed DMA Transfers BetweenTolerant Inputs
1394 and Local Bus RAM, ROM, AUX,or•
Performs the Functionof 1394 Cycle Master Zoomed Video•
Provides 4K Bytesof Configurable FIFO RAM •
Advanced Submicron, Low-Power CMOS•
Provides Five Scatter-Gather DMA Channels Technology•
Provides Software Controlof Interrupt Events •
Packagedina 176-Pin PQFP (PGF)•
Provides Four General-Purpose
Input/OutputsThe TSB12LV21B (PCILynx-2) providesa high-performance IEEE 1394-1995 interface with the capabilityto
transfer data between the 1394 PHY-link interface, the PCI bus interface, and external devices connectedto the
local bus interface. The 1394 PHY-link interface provides the connectionto the 1394 physical layer device;itis
supportedby the onboard link layer controller (LLC). The LLC provides the control for transmitting and receiving
1394 packet data between the FIFO and PHY-link interfaceat ratesof 100 Mbit/s, 200 Mbit/s, and 400 Mbit/s.
The link layer also provides the capabilityto receive status from the physical layer device andto access the
physical layer control and status registersby the application software. The PCILynx–2 complies with PCI Local Bus Specification, Revision 2.1 IEEE Standard fora 1394-1995 High Performance Serial Bus IEEE Standard 1212-1991 IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses internal 4Kbyte-memory can be configuredas multiple variable-size FIFOs, eliminating the need for external
FIFOs. Separate FIFOs are user configurable to support 1394 receive, asynchronous transmit, and
isosynchronous transmit transfer operations.
The PCI interface supports 32-bit burst transfersupto33 MHz andis capableof operating bothasa master anda target device. Configuration registers can be loaded from an external serial EEPROM, allowing board and
system designersto assign their own unique identification codes. An autoboot mode allows data-moving
systems (suchas docking stations)tobe designedto operateon the PCI bus without the need fora host CPU. controller uses packet control list (PCL) data structuresto control the transferof data and allow the without host CPU intervention. These PCLs can residein PCI memoryorin memory thatis
locations,to provide the highest performance,orto nonaligned locations,to provide the best memory use.
