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TSB12LV01B-TSB12LV01BPZT-TSB12LV01BPZTG4
High Performance 1394 3.3V Link Layer for Telecom, Embedded & Industrial App.,32-Bit I/F, 2kb FIFO
www.ti.com
FEATURES
DESCRIPTION
TSB12LV01B
SLLA212–JUNE 2006
IEEE 1394-1995 High-Speed Serial-Bus Link-Layer Controller Physical-Link Interface Link Core – Compatible With Texas Instruments
Physical Layer Devices (PHYs)– Supports Provisionof IEEE 1394-1995
(1394) Standard for High-Performance – Supports Transfer Speedsof 100, 200, and
Serial Bus 400 Mbits/s Transmits and Receives Correctly – Timing Compliant with IEEE 1394a–2000
Formatted 1394 Packets •
Host Bus Interface Supports Asynchronous and Isochronous – Provides Chip Control With DirectlyData Transfers Addressable Registers Performs Functionof 1394 Cycle Master –Is Interrupt Drivento Minimize Host Polling Generates and Checks 32-Bit CRC – Hasa Generic 32-Bit Host Bus Interface Detects Lost Cycle-Start Messages •
General Contains Asynchronous, Isochronous, and – Operates Froma 3.3-V Power Supply While
General-Receive FIFOs Totaling 2K Bytes Maintaining 5-V Tolerant Inputs Manufactured With Low-Power CMOS
Technology 100-Pin PZT Package for 0°Cto 70°C and
-40°Cto 85°C(I Temperature) OperationThe TSB12LV01Bisan IEEE 1394-1995 standard (from now on referredto onlyas 1394) high-speed serial-bus
link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B providesa
high-performance IEEE 1394-1995 interface with the capabilityof transferring data between the 32-bit host bus,
the 1394 PHY-link interface, and external devices connectedto the local bus interface. The 1394 PHY-link
interface provides the connectionto the 1394 physical (PHY) layer device andis supported by the link-layer
controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO
and PHY-link interfaceat ratesof 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and
receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check
(CRC). The TSB12LV01Bis capableof being cycle master and supports receptionof isochronous data on two
channels. TSB12LV01B hasa generic 32-bit host bus interface, which will connectto most 32-bit hosts. The
LLC also provides the capabilityto receive status from the physical layer device andto access the physical layer
control and status registers by the application software. An internal 2K-byte memoryis provided that can be
configuredas multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs canbe
user configuredto support general 1394 receive, asynchronous transmit, and isochronous transmit transfer
operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF),
asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).
The TSB12LV01Bisa revisionof the TSB12LV01A, with feature enhancements and corrections.Itis pin for pin with the TSB12LV01A with the restrictions noted below.Itis also software compatible with the noted below. items have been fixed, and the following feature enhancements have been made: pin changes have been made. Referto TSB12LV01Ato TSB12LV01B Transition Document,TI
literature number SLLA081 dated May 2000.
