TSA1001CFT ,10-BIT, 25MSPS, 35MW A/D CONVERTERNCD9 (MSB)DRORVCCBVCCBGNDBGNDBVCCBGNDBNCDGNDNC NCOEBDGNDDFSBCLKAVCCDGNDAVCCDVCCAGNDDV ..
TSA1001IF ,10-BIT, 25MSPS, 35MW A/D CONVERTERABSOLUTE MAXIMUM RATINGS Symbol Parameter Values Unit1)AVCC 0 to 3.3 VAnalog Supply voltage 1)DVC ..
TSA1001IFT ,10-BIT, 25MSPS, 35MW A/D CONVERTERapplications, the26AVCC D711TSA1001 only dissipates 35mW at 25Msps. When25AVCC 12 D8running at lowe ..
TSA1002CFT ,10-BIT, 50MSPS, 50MW A/D CONVERTERBLOCK DIAGRAM VREFP+2.5VGNDAVINReferencestage stageINCM stageIPOLcircuit 1 2 nVINBVR ..
TSA1201IF ,12-BIT, 50MSPS, 150MW A/D CONVERTERNCD11 (MSB)DRORVCCBEVCCBEGNDBEGNDBEVCCBIGNDBINC DGNDSRCNC OEBDGNDDFSBCLKAVCCDGNDAVCCD ..
TSA1203IF ,DUAL-CHANNEL, 12-BIT, 40MSPS A/D CONVERTERD1GNDBID0(LSB)DVCCVCCBEDGNDGNDBESELECTVCCBICLKVCCBIDGNDOEBDVCCAVCC AVCCAVCCAGNDINCMIINCMQREFMIREFMQ ..
UAA4713DP ,MOTION DETECTOR INTERFACEapplications.The device can be usedprogrammable timer will start and switch a lampin a wide range o ..
UAA4713FP ,MOTION DETECTOR INTERFACEABSOLUTE MAXIMUM RATINGSSymbol Parameter Test Conditions UnitI7 AC Supply Current 60 mAI7 Peak Curr ..
UAF1780 ,DUAL 2A LOW DROP OUT INTELLIGENT POWER SWITCHCO SGS-THOMSON
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DUAL 2 A LOW DROP OUT INTELLIGENT P ..
UAF41 , DIODE-PENTODE
UAF42AP ,Universal Active Filter.PIN CONFIGURATIONSP PACKAGEU PACKAGEPDIP-14SOIC-16(TOP VIEW)(TOP VIEW)Low-Pass V 1 14 Frequency Ad ..
UAF42AP ,Universal Active FilterMAXIMUM RATINGSOver operating free-air temperature range unless otherwise noted.UAF42 UNITPower Sup ..
TSA1001CF-TSA1001CFT-TSA1001IF-TSA1001IFT
10-BIT, 25MSPS, 35MW A/D CONVERTER
10-bit A/D converter in deep submicron CMOS technology � Ultra low power consumption: 35mW @
25Msps (10mW @ 5Msps)� Single supply voltage: 2.5V� Input range: 2Vpp differential� 25Msps sampling frequency� ENOB=9.7 @ 25Msps, Fin=5MHz� SFDR typically up to 80dB @ 25Msps,
Fin=5MHz� Built-in reference voltage with external bias
capability� Pinout compatibility with TSA0801, TSA1002
and TSA1201
DESCRIPTIONThe TSA1001 is a 10-bit, 25Msps sampling fre-
quency Analog to Digital converter using a CMOS
technology combining high performances and
very low power consumption.
The TSA1001 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and achieve 9.7 effective bits at
Fs=25Msps, and Fin=5MHz.
Especially designed for portable applications, theTSA1001 only dissipates 35mW at 25Msps. When
running at lower sampling frequencies, even lower
consumption can be achieved.
A voltage reference is integrated in the circuit to
simplify the design and minimize external compo-
nents. It is nevertheless possible to use the circuit
with an external reference.
The output data can be coded into two different
formats. A Data Ready signal is raised as the data
is valid on the output and can be used for synchro-
nization purposes.
The TSA1001 is available in commercial (0 to
+70°C) and extended (-40 to +85°C) temperature
range, in a small 48 pins TQFP package.
APPLICATIONS Portable instrumentation� Video processing� Medical imaging and ultrasound� High resolution fax and scanners� Digital communications
ORDER CODE
PIN CONNECTIONS (top view)
PACKAGE
TSA100110-BIT, 25MSPS, 35mW A/D CONVERTER
TSA1001
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS 1) Condition VRefP-VRefM>0.3V
BLOCK DIAGRAM 1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages
must never exceed -0.3V or VCC+0V
TSA1001
PIN CONNECTIONS (top view)
PIN DESCRIPTION
TSA1001
ELECTRICAL CHARACTERISTICSAVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
TIMING DIAGRAM
TSA1001
CONDITIONS:AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
REFERENCE VOLTAGE 1). See parameters definition for more information
1). Not fully tested over the temperature range. Guaranteed by sampling.
TSA1001
CONDITIONS:AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
DIGITAL INPUTS AND OUTPUTS
ACCURACY
POWER CONSUMPTION1). Rpol= 25KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF
2). Not fully tested over the temperature range. Guaranteed by sampling.
TSA1001
CONDITIONS:AVCC = DVCC = 2.5V, Fs= 25Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS1). Rpol= 25KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF
2). Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranteed by sampling.
TSA1001
DEFINITIONS OF SPECIFIED PARAMETERS
STATIC PARAMETERSStatic measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 25Msps, which is high enough to fully
characterize the test frequency response. The in-
put level is +1dBFS to saturate the signal.
Differential Non Linearity (DNL)The average deviation of any output code width
from the ideal code width of 1LSB.
Integral Non linearity (INL)An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERSDynamic measurements are performed by
spectral analysis, applied to an input sinewave of
various frequencies and sampled at 25Msps.
Spurious Free Dynamic Range (SFDR)The ratio between the amplitude of fundamental
tone (signal power) and the power of the worst
spurious signal (not always an harmonic) over the
full Nyquist band. It is expressed in dBc.
Total Harmonic Distortion (THD)The ratio of the rms sum of the first five harmonicdistortion components to the rms value of the
fundamental line. It is expressed in dB.
Signal to Noise Ratio (SNR)The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Signal to Noise and Distortion Ratio (SINAD)Similar ratio as for SNR but including the harmonicdistortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A0 /FS)
The ENOB is expressed in bits.
Analog Input BandwidthThe maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delay
Delay between the initial sample of the analog in-
put and the availability of the corresponding digitaldata output, on the output bus. Also called data la-
tency. It is expressed as a number of clock cycles.
TSA1001
Static parameter: Integral Non LinearityFs=25MSPS; Fin=1MHz; Icca=11mA; N=131072pts
Static parameter: Differential Non LinearityFs=25MSPS; Fin=1MHz; Icca=11mA; N=131072 pts
Linearity vs. FsFin=1MHz; Rpol adjustment
Distortion vs. FsFin=1MHz; Rpol adjustment
TSA1001
Linearity vs. Fs Fin=15MHz; Rpol adjustment
Linearity vs. FinFs=25MSPS; Icca=11mA
Linearity vs.TemperatureFs=25MSPS; Icca=11mA; Fin=5MHz
Distortion vs. Fs Fin=15MHz; Rpol adjustment
Linearity vs. FinFs=25MSPS; Icca=11mA
Distortion vs. TemperatureFs=25MSPS; Icca=11mA; Fin=5MHz;
